Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-11-05
2003-03-18
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000, C341S118000
Reexamination Certificate
active
06535154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to improvements in digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) utilizing oversampled operation internally. More particularly, the present invention relates to significantly simplified circuitry for DACs and ADCs using dynamic element matching techniques without a reduction in signal quality.
2. State of the Art
Modern semiconductor technologies require ever smaller feature sizes and circuits. While digital processing of signals makes the achievement of higher performance and smaller circuits possible, the trend to smaller circuits makes the design of low noise analog systems more difficult. Effective conversion circuitry between analog and digital systems therefore is becoming more important as semiconductor technologies shrink. Digital-to-analog converters (“DAC”s) and analog-to-digital converters (“ADC”s) are widely used in electronic devices to convert signals between analog and digital circuitry.
Mismatches in DAC and ADC elements in audio and other systems can create harmonic distortion (i.e., linearity errors) in the signals carried therein. These errors are reduced or eliminated by employing conventional dynamic element matching (DEM) algorithms which convert linearity errors into a noise signal uncorrelated to the input signal. Noise-shaped DEM techniques are useful in oversampled converters, allowing linearity errors to be translated into noise that is pushed toward out-of-band regions of the frequency spectrum.
The frequency spectrum of a signal is a frequency-domain interpretation of a signal and refers to the frequencies which are detected by or of interest to the person or circuit receiving the signal. This is also called the “signal band.” In the case of audio DACs, ultimately the only frequencies of concern are those in the audio signal band which can be heard by people, typically assumed to be about 20 Hz to 20 kHz. However, audio DAC circuitry is capable of running at much higher speeds and has some amount of signal energy from DC to far into the MHZ range. An oversampling audio DAC, which conventionally uses a delta-sigma modulator, makes use of the regions in the frequency spectrum outside of the audio signal band, i.e., below 20 Hz and above 20 kHz, in order to provide a low noise, high quality signal in the audio signal band (20 Hz to 20 kHz). However, delta-sigma modulators may generate additional quantization noise outside the signal band. Dynamic element matching (DEM) techniques also take advantage of this to provide good quality conversion in the signal band region even in the presence of a mismatch, while causing more noise in out-of-band regions.
Existing DEM techniques use multiple unit DAC elements and require an exponential increase in circuit complexity as the number of bits in the DAC increases. This is further explained with reference to
FIGS. 1A
,
1
B and
2
. A 4-bit DAC
2
having a prior art decoder/processor block
4
is shown in FIG.
1
A.
FIG. 1B
shows an implementation of DAC
2
of
FIG. 1A
according to the present invention. The decoder/processor circuitry
4
is used to convert the 4-bit input B
0
,
1
,
2
,
3
into the 15 control bits C
0
,
1
,
2
. . .
14
needed to control the individual DAC unit weighting elements
6
.
FIG. 2
shows one possible implementation of the prior art digital-to-analog converter of
FIG. 1A
including a detailed implementation of decoder/processor
4
and a back end analog DAC circuit
18
which can be the same as the circuit
2
shown in FIG.
1
B. Note that the analog output
19
in
FIG. 2
may be a differential analog output signal, which in the implementation shown in
FIG. 1B
actually is provided using two conductors
19
A,
19
B, even though the differential analog output signal is shown in
FIG. 2
as only a single line
19
.
The 4-bit DAC
2
includes
15
DAC unit weighting elements
6
-
0
,
1
,
2
. . .
14
, each receiving a corresponding control bit C
0
,
1
,
2
. . .
14
, respectively, that determines if its (+) output is set positive or negative. The (−) output of each of DAC unit weighting elements
6
-
0
,
1
,
2
. . .
14
is opposite to its (+) output. For the DAC
2
shown in
FIG. 1B
, the weight of each of the (−) outputs
7
-
0
,
1
,
2
. . .
14
is ½, and the weight of each of the (+) outputs
9
-
0
,
1
,
2
. . .
14
also is ½. If the input control bit C for an individual DAC unit element is equal to a “1”, its (+) output signal is equal to ½ and its (−) output signal is equal to −½. If the input control bit C for an individual DAC unit element is equal to a “0”, its (+) output signal is equal to −½ and its (−) signal is equal to ½. By summing the (+) outputs together by means of summer
11
and summing the (−outputs together by means of summer
13
, the outputs Out
31
and Out
+
are produced on output conductors
19
A and
19
B, respectively, and each has a value which varies from −7.5 to +7.5. Note that for the DAC to produce a differential output of value zero for a particular code, (i.e., Out
31
and Out
+
are equal), the circuitry will need to be modified, such as by subtracting ½ from Out
+
and adding ½ to Out
−
at all times. That is, if ½ is subtracted from Out
+
and added to Out
−
at all times, then a zero level differential output is obtained. Note that the new range of values of Out
+
is from −7 to +8. The differential output of the DAC, defined as the difference Out
+
−Out
−
, now may range from −16 to +14. However, for the purposes of the remaining description herein, this modification to obtain a zero level differential output is not assumed.
Referring to
FIG. 2
, a digital filter modulator, referred to herein as a “MOD”, typically including a digital delta sigma modulator, multiple integrators, summers and gain paths, is used as part of the DEM processing portion of the decoder/processing block
4
in the prior art to generate a multi-bit output. Each digital filter modulator
8
has a “D” input which receives a digital input signal. Each digital filter modulator
8
also has a C input or control input, and produces a sum on an output conductors
17
. The MOD blocks are just the front ends of digital delta sigma modulators (DDSMs) with their D inputs being where the digital input signal is applied, and their C inputs being where the fed-back quantized signal is applied. Typically, there are internal integrators, sum/difference circuits, and gain paths.
FIG. 2
illustrates a block diagram of a processing section used in prior art DACs with dynamic element matching. In
FIG. 2
, each MOD filter block
8
-
0
,
1
,
2
. . .
13
,
14
is preceded by a corresponding scaling block
10
-
0
,
1
,
2
. . .
13
,
14
, respectively, which scales the corresponding input signal C
0
,
1
,
2
. . .
14
by a factor &agr;. In the example shown, if the input signal C for a particular digital filter modulator MOD
8
is “0”, the value of its output
17
is −8, and if the input signal C is 1, the value of the digital filter modulator output
17
is +7. This scaling is determined by the range of values possible from the B
0
,
1
,
2
,
3
inputs. In this case, the B
0
,
1
,
2
,
3
inputs are interpreted by the MOD blocks as signed digital numbers with a range from −8 to +7. A sort/decision circuit
12
receives the 4-bit input signal B
0
,
1
,
2
,
3
and interprets it differently, by first subtracting the minimum signed digital number this input could represent (which in this case is −8) from the actual signed digital number. This results in a new number which is only non-negative and is referred to as the code X. The sort/decision circuit
12
then sets X of the C input bits equal to “1”, and the rest equal to “0” . The sort/decision circuit
12
also sorts the sum inputs
17
from highest value
Brady W. James
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Howard L.
LandOfFree
Enhanced noise-shaped quasi-dynamic-element-matching technique does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced noise-shaped quasi-dynamic-element-matching technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced noise-shaped quasi-dynamic-element-matching technique will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3005557