Static information storage and retrieval – Addressing – Counting
Patent
1997-08-07
1999-05-04
Nelms, David
Static information storage and retrieval
Addressing
Counting
36523002, G11C 800
Patent
active
059011114
ABSTRACT:
A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.
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McLaury Loren L.
Morgan Donald M.
Micro)n Technology, Inc.
Nelms David
Tran M.
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