Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2002-01-17
2004-07-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S052000, C439S637000
Reexamination Certificate
active
06765812
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to memory module architectures and in particular relates to an enhanced memory module configuration to provide additional flexibility in memory module applications in conjunction with PowerPC and other system applications.
2. Discussion of Related Art
Present-day computing systems often utilize standardized memory modules to add memory capacity to a system. A memory module is generally comprised of a number of memory chips mounted on a printed circuit card adapted for insertion into a standard carrier or socket connector. The module is easily added or removed from a system to permit flexible configuration of memory capacity. The module and socket adhere to a standardized pin assignment for exchange of signals between a system bus and the memory chips. Signals are routed from the carrier connector to the memory chips in accordance with the particular standard used for the module and the particular memory chips selected by the memory module manufacturer.
A number of standards are defined for such modules. Exemplary of one such standard is a so-called 144-pin Small Outline DIMM module (also referred to as “SO-DIMM”) as defined by the JEDEC JESD21-C standard specification (available online at www.jedec.org). The 144-pin SO-DIMM provides a convenient, compact design for use in space-constrained applications such as portable computing devices or embedded systems. The module is a small printed circuit card with memory devices mounted thereon and one edge that provides electrical connectivity of up to 144 signals when the module is inserted into a mated connector on the main system board (i.e., the system motherboard). The printed circuit card signal traces connect standard signals assigned to the 144 pins of the module's edge connector to appropriate pins of the memory chips mounted thereon. A memory controller on the system board exchanges these standard memory control signals with the module through the mated connector.
In particular, the 144-pin standard module provides for memory chips to be mounted on one or both physical sides of the printed circuit board. A select signal is typically applied to the module by a CPU or memory controller to select the memory chips on one or the other side of the memory module for exchange of data and control signals. This select signal is often referred to as a “row select” signal in regards to the 144-pin standard configuration. When the “front” side is selected by the memory controller, only those chips respond to the exchange of signals with the system board. Similarly, when the “back” side is selected, only those memory chips respond to the memory controller signals.
Most memory modules and carriers define signal connections for standard DRAM memory devices (dynamic random access memory) mounted on the module. Such signal definitions include signals common to most DRAM devices including, in particular, SDRAMs (synchronous DRAM devices). Other forms of memory, in particular asynchronous memories, are not generally accommodated by the standard signal paths provided for on the standard DIMM memory module. For example, present standard DIMM modules such as the 144-pin SO-DIMM do not support so-called Flash memory devices. Neither are static RAMs (SRAM devices) generally supported by such standard DIMM modules.
This presents a particular problem to embedded applications where a wide variety of memory devices are often applied to resolve special problems in particular applications. For example, the non-volatile nature of Flash memory devices makes them particularly useful in many embedded applications for storage of computer program instructions while a standard SDRAM may be used for storage and retrieval of program data. Since no single standard memory module supports such a variety of memory devices, it is often necessary to design embedded applications for multiple memory module architectures and associated busses and/or to redesign the system as the memory requirements change or new memory components become available. For example, it is common in many such embedded applications to design a first memory bus for exchange of signals with synchronous memory components (i.e., SDRAMs) and a separate slower memory bus for asynchronous devices such as Flash or static RAMs. This added complexity adds cost and size to the design and complicates portability of a system design to multiple applications that may have different needs for memory configuration.
Furthermore, it is a problem for many such memory module designs to be used in embedded applications where there is significant vibration or mechanical shock. Standard DIMM modules insert into a mated socket at one edge. Some DIMM modules are designed to latch or lock on two other sides of the module. However, the edge opposing the socket is often unsupported and may lead to failures in applications of high vibration and mechanical shock. In particular it has been found that under certain common vibrational modes, the SO-DIMM module may twist about a pivot point at the key in the DIMM socket. Sufficient twisting due to such vibration can lead to unacceptable, premature DIMM module failure.
It is evident from the above discussion that a need exists for an improved memory module design that permits a wider variety of memory device types to be used in a standard DIMM socket on a common bus. It is further evident that a need exists for an improved mechanical design for a memory module that better withstands high vibration environments or environments that may entail significant mechanical shock.
SUMMARY OF THE INVENTION
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a modified memory module design that accommodates a wider variety of memory devices. In particular, the modified memory module architecture of the present invention redefines a number of standard signals to permit utilization of Flash and static memory components in a DIMM module while maintaining backward compatibility to standard DRAM and SDRAM DIMM modules. Still more specifically in one exemplary preferred embodiment, the present invention preferably utilizes row select signals (“CS(0:1)”) of a standard 144-pin SO-DIMM module to provide requisite select and control signals for Flash and static memory devices.
Still more specifically, where a memory controller is capable of multiplexing both synchronous and asynchronous memory device accesses over the same signal paths, the present invention permits use of Flash and other special memory modules that are physically compatible with SO-DIMM configurations in conjunction with typical SDRAM (or other DRAM) SO-DIMM modules over the same multiplexed memory controller bus signals. For example, the Motorola family of embedded PowerPC microcomputers (MPC824x and others) includes such a memory controller—specifically the MPC107 memory controller. The MPC106 or MPC107 memory controller device provides such a memory controller feature and is integrated into the MPC824x chip die and available as a separate integrated circuit component. Systems using the MPC106 or MPC107 memory controller as a separate component may also benefit from the present invention. Further, other similarly featured memory controllers are commercially available and systems using such similarly featured memory controller may beneficially apply the features of the present invention.
In one particularly useful embodiment, the signals of a JEDEC JESD21-C 144-pin SO-DIMM standard memory module are modified to enable support of Flash and SRAM memory devices on the modified standard DIMM module. In particular, the chip select (row select) signals are modified to provide the requisite selection of Flash and SRAM memory components in addition to standard SDRAM (or DRAM) memory components. Setting of jumpers on the system board preferably indicate the presence of such additional memory device types in the SO-DIMM sockets of the system and adapt the signal exchange with a memory controller to
Honeywell International , Inc.
Le Vu A.
Nguyen N.
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