Classifying – separating – and assorting solids – Sorting special items – and certain methods and apparatus for... – Condition responsive means controls separating means
Reexamination Certificate
2002-02-21
2003-10-14
Nguyen, Tuan N. (Department: 3653)
Classifying, separating, and assorting solids
Sorting special items, and certain methods and apparatus for...
Condition responsive means controls separating means
C324S1540PB
Reexamination Certificate
active
06633014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the grading and sorting of semiconductor devices and, more specifically, singulated memory devices, using modular “plug-in” sort algorithms during an automated device sort process.
2. State of the Art
It is conventional to characterize or qualify singulated semiconductor devices, including memory devices, for compliance with certain criteria in order to determine their suitability or lack thereof for different potential uses. In the past, several different test programs have been used to sort all of the potential grades of memory product such as, for example, All good (Full Array or Profit), DQ/Array partials, Slow (GD) memory, and Audio RAM. Because of the complexity involved in testing each of the memory product types, separate programs have been developed to sort the full array/partials vs. various forms of Audio RAM. This test sequence involves running product (a memory device) through multiple steps: as a device fails to sort to a particular grade in one test program, it is subsequently, sequentially loaded in one or more other test programs, and eventually sorted out to a particular grade, or failed. Using multiple test programs in this way leads to increased test times, excessive part handling, and lost or mis-binned parts due to the over-complexity of the test flow process. Furthermore, maintaining multiple programs for a particular type of memory product also increases work load as well as resource strain on engineering personnel and the systems they are responsible for maintaining and operating.
BRIEF SUMMARY OF THE INVENTION
The device sorting method and apparatus of the present invention solves the aforementioned problems of sorting memory devices into multiple memory grades by eliminating a requirement for multiple passes by the devices through different test programs, unlike the process flow in conventional sorting methods. The inventive method and apparatus also allow for simple modification of precedence rules when business objectives change and it is consequently determined that one particular grade is more valuable or cost-effective than another, previously favored, grade. Furthermore, creating engineering “bins” for screening parts or collecting samples exhibiting certain characteristics is easily facilitated with this flexible binning method.
The sorting method and apparatus of the present invention involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a semiconductor memory device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given memory grade. In addition, the modular approach facilitates modification or refinement of test criteria for a given grade, or development of a new device grade, since only the code for a given modular program must be revised or developed, rather than modifying the main program and flow file.
The potential device grades allowed for a given lot of devices to be tested may be determined at the run time for that lot and loaded into the test controller as part of the test flow file. The order in which the memory grades will be selected, or grade precedence, may also be determined at this point. When tests are included in the test flow which pertain to only a subset of the total grades, these tests may be flagged as “constrained” and will, as a result, only register as “fails” if the device initiating the fail response under test is targeted for one of the applicable (subset) grades. Further, the particular fail bin (the bin where a device is to go if it fails to meet the requirements of all available, i.e., usable, grades) is determined in the test flow file so that any given test or subgroup of tests can be screened or sorted to a unique bin for engineering data and sample collection.
The present invention may be implemented through the use of a commercially available semiconductor device tester under control of a suitably programmed workstation or other controller.
As used herein, the term “memory” or “memory device” includes, by way of example only, dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs) however programmable and erasable, and flash memory.
As noted below, the method of the present invention, while described herein in relationship to testing of memory devices, is applicable to testing of other types of semiconductor devices.
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Nguyen Tuan N.
TraskBritt
LandOfFree
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