Enhanced glitch removal circuit

Details Enhanced glitch removal circuit Enhanced glitch removal circuit

1997-04-11

2000-10-17

Tokar, Michael

Coherent light generators

Particular temperature control

326 26, G01R 2902

Patent

active

061342521

ABSTRACT:
An enhanced glitch eater circuit for eliminating glitch signals occurring within a predetermined period from a raising edge or a falling edge of a signal pulse is comprised of an inverter connected to a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate receiving a latched signal at one input and a delay latched signal at the other input, the latched signal being from the output of the transmission gate. The latched signal may be reset by a transistor.

REFERENCES:
patent: 5151615 (1992-09-01), Egawa
patent: 5194768 (1993-03-01), Lozano
patent: 5723993 (1998-03-01), Cha
patent: 5959465 (1999-09-01), Beat

Affiliated with

Also associated with

Rating

Enhanced glitch removal circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced glitch removal circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced glitch removal circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-476550