Enhanced folded cascade voltage gain cell

Details Enhanced folded cascade voltage gain cell Enhanced folded cascade voltage gain cell

2001-08-14

2003-02-11

Wells, Kenneth B. (Department: 2816)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S258000

Reexamination Certificate

active

06518841

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuit amplifiers and, more specifically, to voltage gain cells employing a folded cascade topology.
BACKGROUND OF THE INVENTION
Voltage gain cells are typically implemented in two stages, as shown in FIG.
2
. The transfer function of the circuit is given by:
V
o
V
i
=
gm
1
gm
2
(
1
)
where V
i
is the voltage input to differential amplifier GM
1
, V
o
is the voltage output of differential amplifier GM
2
, gm
1
is the transconductance of differential amplifier GM
1
, and gm
2
is the trasnconductance of differential amplifier GM
2
.
Some voltage gain cells employ external resistors R
1
and R
2
as shown in
FIG. 3
to set the transconductance value gm of each differential amplifier, where the voltage gain becomes:
 
gm
=1
/R.
  (2)
The voltage gain (i.e., transfer function) for the voltage gain circuit in
FIG. 3
is therefore:
V
o
V
i
=
R
2
R
1
·
(
3
)
When implemented with a folded-cascade topology, a two stage voltage gain cell of the type shown in
FIG. 3
may be implemented by the transistor-level circuit of
FIG. 4
, where only the essential components are shown and the common mode feedback is not included.
The implementation of a folded cascade voltage gain cell which is shown includes a first stage having n-channel transistors MNU
1
and MND
1
receiving the input voltage V
i
through positive and negative inputs IN+and IN−at the gates of transistors MNU
1
and MND
1
. Resistors R
1
are connected between the sources of transistors MNU
1
and MND
1
, and current sources IU
1
and ID
1
are each connected between the source of one of transistors MNU
1
and MND
1
and a ground voltage gnd.
Current source IPUL is connected between the drain of transistor MNU
1
(node NU
1
) and a power supply voltage Vdd. The drain of transistor MND
1
is connected to the source of p-channel transistor MPU
1
(node ND
1
), which receives a reference voltage Vref at a common gate connection with p-channel transistor MPD
1
. The source of transistor MPD
1
is connected to node NU
1
and, through current source IPU
1
, to the power supply voltage Vdd. The drains of transistors MPD
1
and MPU
1
are each connected, through a current source IOD
1
and IOU
1
, respectively, to the ground voltage gnd. The positive and negative output signals OUT+and OUT−which form the output voltage V
o
are drawn from the drains of transistors MPD
1
and MPU
1
, and couple the first and second stages of the voltage gain cell.
Within the second stage, output signals OUT+and OUT−are connected to the drains of p-channel transistors MPU
2
and MPD
2
, respectively, and to the gates of n-channel transistors MND
2
and MNU
2
, respectively. The drain of transistor MNU
2
(node NU
2
) is connected to the source of transistor MPD
2
and to through current source IPU
2
to the power supply voltage Vdd. The drain of transistor MND
2
(node ND
2
) is connected to the source of transistor MPU
2
and to through current source IPD
2
to the power supply voltage Vdd. Resistors R
2
are connected between the sources of transistors MNU
2
and MND
2
, and the sources of transistors MNU
2
and MND
2
and the drains of transistors MPD
2
and MPU
2
are each connected through one of current sources IU
2
, ID
2
, IOD
2
and IOU
2
to the ground voltage gnd.
Multistage folded cascade voltage gain cells of the type shown in
FIG. 4
consume significant power and, because of the number of internal nodes, contain a corresponding number of poles, which limits operational bandwidth. There is, therefore, a need in the art for a folded cascade voltage gain cell having fewer stages and transistors.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an integrated circuit, a folded cascade voltage gain cell implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit's operation contains a smaller number of poles, and bandwidth is improved.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.


REFERENCES:
patent: 5187680 (1993-02-01), Engeler
patent: 5729178 (1998-03-01), Park et al.
“A 4-Hmz CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” Francois Krummenacher and Norbert Joehl, IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Jun. 1988.
“A Large-Signal Very Low-Distortion Transconductor for High-Frequency Continuous-Time Filters,” Jose Silva-Martinez, Michel S. J. Steyaert and Willy M.C. Sansen, IEEE Journal of Solid-State Circuits, vol. 26, No. 7, Jul. 1991.
“A 10.7-MHz 68-dB SNR CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” Jose Silva-Man Michel S. J. Steyaert and Willy M.C. Sansen, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.

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