Enhanced error detection scheme for instruction address sequenci

Details Enhanced error detection scheme for instruction address sequenci Enhanced error detection scheme for instruction address sequenci

1989-10-20

1993-08-31

Baker, Stephen M.

Excavating

371 494, G06F 1128

Patent

active

052415473

ABSTRACT:
A control store holding a large number of instruction words is accessed by a sequence of instruction addresses. An intercooperating system uses a test condition select logic unit and a next address select logic unit are combined with address sequence error detection logic in order to develop an error flag signal should there be some error in the sequence of the actual instruction address data supplied to the control store.

REFERENCES:
patent: 3192362 (1965-06-01), Cheney
patent: 3387262 (1968-06-01), Ottaway et al.
patent: 3518413 (1970-06-01), Holtey
patent: 4019033 (1977-04-01), Parmet
patent: 4074229 (1978-02-01), Prey
patent: 4108359 (1978-08-01), Proto
IEEE Trans. On Computers, Cook et al., "Design of a Self-Checking Microprogram Control", vol. C-22, Mar. 1973, pp. 255-262.

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