Enhanced efuses by the local degradation of the fuse link

Details Enhanced efuses by the local degradation of the fuse link Enhanced efuses by the local degradation of the fuse link

2000-05-30

2002-04-09

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to nonconductive state

C438S131000, C257S529000, C257S530000

Reexamination Certificate

active

06368902

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to fuses on integrated circuit boards and specifically to fuses with controlled and predictable areas of degradation.
Redundancy in integrated circuit memories is part of the current chip manufacturing strategy to improve yield. By replacing defective cells with duplicate or redundant circuits on chips, integrated circuit memory yields are significantly increased. The current practice is to cut or blow conductive connections (fuses), thereby allowing the redundant memory cells to be used in place of nonfunctional cells. In the manufacture of integrated circuits, it is also common practice to provide for customization of chips and modules to adapt chips to specific applications. By selectively blowing fuses within an integrated circuit having multiple potential uses, a single integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Typically, fuses or fusible links are incorporated in the integrated circuit design, and these fuses are selectively blown, for example, by passing an electrical current of sufficient magnitude to cause them to open. Alternatively, a current that is weaker than the current required to entirely blow the fuse can be applied to the fuse in order to degrade the fuse and increase the resistance through the fuse. The process of selectively blowing or degrading fuses is often referred to as “programming.” An alternative to blowing fuse links with a current is to open a window above each fuse to be broken, use a laser to blow the fuses, and then fill the windows with a passivation layer.
FIGS. 1
a
through
1
c
show a conventional fuse generally at
10
.
FIGS. 1
a
and
1
b
show a top plan view and a cross section, respectively, of a conventional fuse prior to programming.
FIG. 1
c
shows the same cross section shown in
FIG. 1
b
after the fuse has been programed. The fuse comprises two contacts
16
in electrical contact with a conducting silicide layer
14
, which is disposed on a polysilicon layer
18
. The fuse is generally covered with an insulative passivation layer (not shown). The silicide layer
14
and the polysilicon layer
18
are arranged in a stack, which is disposed on an insulative layer
12
. The insulative layer
12
is typically an oxide layer, which itself has been deposited or grown on a substrate
20
. The substrate
20
is typically monocrystalline silicon.
Referring now to
FIG. 1
b,
current flowing through the fuse will generally proceed from one contact
16
, through the silicide layer
14
, to the other contact
16
. If the current is increased to a level that exceeds the threshold current value of the fuse, the silicide layer
14
will melt, effectively opening the circuit. The resulting “blown” fuse is shown in
FIG. 1
c.
The melted silicide forms agglomerations
24
on either side of a discontinuity
22
. The fuse shown in
FIGS. 1
a
through
1
c
can be modified by altering the characteristics of the underlying polysilicon layer
18
. If the polysilicon layer
18
is heavily doped, for example, it can then serve as a higher resistance path through which current will flow after a discontinuity
22
is created in the silicide layer
14
.
The fuse design described above, however, does not allow for reliable localization of the discontinuity
22
in the silicide layer
14
. Since the process of melting the silicide layer
14
generates significant and potentially damaging heat, it is desirable to reduce the area in which the discontinuity
22
is potentially formed, to reduce the energy required to program the fuse, or to otherwise reduce the potential for damage to adjacent components when the fuse is programed. Attempts to localize the discontinuity
22
to a predefined region of the silicide layer
14
have included narrowing regions of the silicide to form a narrowed region (forming a “neck”). Alternatively, conventional attempts to minimize damage have included the physical isolation or containment of the fuse within the integrated circuit.
Conventional fuse designs, however, have not eliminated the unwanted damage caused by blowing a fuse, or have added cost or undesirable design qualities to the final product. What is needed in the art is a fuse that is fabricated such that programming of the fuse will result in reproducible degrading and melting of the silicide layer
14
at a defined point between the contacts
16
using less energy than conventional techniques.
BRIEF SUMMARY OF THE INVENTION
The above-described and other disadvantages of the prior art are overcome or alleviated by the fuse structure of the present invention, which comprises a polysilicon layer, a conductive layer disposed on the polysilicon layer, and a covering layer disposed on the conductive layer, wherein the covering layer comprises a first material and a region of filler material comprising a filler material disposed in the first material, and wherein the filler material is in contact with the conductive layer.
The present invention is also a method for making the above-described fuse. The process entails forming a polysilicon layer, forming a conductive layer on the polysilicon layer, forming a covering layer on the conductive layer, wherein the covering layer comprises a first material, and masking with a first photoresist, patterning, and etching to define a stack comprising the polysilicon layer, the conductive layer, and the covering layer. The stack is then masked with a second photoresist, patterned, and etched to define a gap in the covering layer. Then, the gap is filled with a filler material to form a region of filler material, wherein the region of filler material is in contact with the conductive layer.
The above-described and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description, drawings, and appended claims.


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IBM Technical Disclosure Bulletin; Pub No. 1, Jun. 1991 “Improved Silicide Fuses for VLSI Circuits”.

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