Enhanced DLL phase output scheme

Details Enhanced DLL phase output scheme Enhanced DLL phase output scheme

2007-10-16

2007-10-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000

Reexamination Certificate

active

11297040

ABSTRACT:
A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.

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patent: 6741109 (2004-05-01), Huang et al.
patent: 7157949 (2007-01-01), Chen et al.
patent: 7199625 (2007-04-01), Chung
patent: 2001/0052804 (2001-12-01), Hasegawa
patent: 2002/0061088 (2002-05-01), Kon
patent: 2004355081 (2004-12-01), None

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