Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-02-29
2002-03-12
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter compensation
C455S138000
Reexamination Certificate
active
06356217
ABSTRACT:
CROSS REFERENCE TO RELATED DOCUMENTS
This application is related to patent application U.S. Pat. No. 6,225,848 by Tilley, et al., entitled “Method and Apparatus for Settling and Maintaining a DC Offset,” which is a continuation-in-part of pending application Ser. No. 09/290,564 filed Apr. 13, 1999, Tilley, et al., entitled “Method and Apparatus for Settling a DC Offset,” and also related to patent application Ser. No. 09/515,288 by Charles R. Ruelke, entitled “DC Offset Correction Loop for Radio Receiver,” and Ser. No. 09/515,834 by Ferrer, et al., entitled “DC Offset Correction Adaptable to Multiple Requirements,” filed concurrently herewith, assigned to Motorola, Inc., and incorporated herein by reference.
TECHNICAL FIELD
This invention relates to techniques and apparatus for rapidly correcting for DC offsets in electronic circuits.
BACKGROUND OF THE INVENTION
In certain applications for DC offset correction, there is a requirement that the speed of settling the offset correction loop be very fast. For example, in GSM radio receivers, the DC offset correction loop must be settled to within ±30 mV within 400 &mgr;S at the output of the baseband filter. This is a very stringent requirement to be met. Once the loop is settled, even small changes in DC offset can present problems such as saturation of the baseband signal path.
In the above cross-referenced patent application, a binary search method is used to correct DC offset in an electronic circuit. The technique described is particularly useful when applied to a Zero IF (ZIF) or a Direct Conversion Radio Receiver (DCR). The techniques can also be used in other applications including radio transmitters. In this binary search technique, the sign of the DC offset is used to determine whether a correction made via a digital to analog converter (DAC) is to be incremented or decremented in accordance with a binary search algorithm in order to correctly compensate for the DC offset. This process operates very quickly when compared with more conventional analog techniques. However, the bandwidth of the baseband filters in the signal path limits the speed with which the correction can be accomplished. Each time the DAC is incremented during the binary search process, it essentially applies a step voltage function to the input of the baseband signal path. This step function will produce a transient response from the baseband filters (and other circuitry) which has to settle before the next step in the correction process takes place. The settling of the filters in response to the DAC's step by step correction of the DC offset places a limitation on how fast the baseband DC offset can be corrected. Accordingly, there is a need for even faster techniques for settling out baseband DC offset, particularly in radio receivers.
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Ferrer Enrique
Salvi Raul
Tilley Keith A.
Lamb James M.
Scutch Frank A.
Vaas Randall S.
Williams Howard L.
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