Enhanced chip scale package for wire bond dies

Details Enhanced chip scale package for wire bond dies Enhanced chip scale package for wire bond dies

2002-02-19

2004-03-23

Graybill, David E. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S773000, C257S774000, C257S779000, C257S780000, C257S738000

Reexamination Certificate

active

06710438

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuits, and particularly relates to chip scale packaging of wire bonded integrated circuits.
Packaging technology represents an enabling element in the ongoing microelectronics revolution. As integrated circuits have shrunk, so too have the physical packages carrying these devices. Various techniques are used to minimize the physical space required for integrated circuits, and to accommodate the increasingly high number of signal connections associated with dense integrated circuit devices.
Common approaches include various chip-on-glass and chip-on-board technologies. In these, an integrated circuit die is mounted directly on a primary circuit substrate, covered only by a minimal amount of epoxy or resin. While offering certain advantages in high-volume manufacturing environments, integrated circuit devices of this nature place significant challenges on handling and testing.
Other approaches strike a balance between physical size and the practical considerations of handling and testing. So-called “chip scale packages” (CSPs) attempt to provide physical packaging for integrated circuit die without increasing the total physical size substantially beyond that of the actual die. Ideally, such packages remain as small as possible while still providing relatively robust protection for the die itself.
Chip scale packaging techniques may incorporate wire bond technology. With wire bond technology, fine wire bonds taken from signal connection points on the die are arrayed as “flying leads,” usually around the perimeter edges of the die. These wire bonds are bonded to corresponding connection points, such as wire bond fingers, on the top surface of a chip carrier on which the die is mounted.
The chip carrier functions much like a printed circuit board, providing a rigid (or sometimes flexible) platform that can be readily handled and more easily mounted to a larger circuit board carrying other electrical or electronic circuits. Essentially, the chip carrier provides practical access to the electrical interconnections of the die it carries.
Typically, the chip carrier comprises a substrate with a top layer providing signal and ground connections for interconnecting with corresponding electrical connections on the die. The carrier's bottom side usually carries corresponding connection points, which may be soldered to corresponding connections on the primary circuit board. Generally, these connection points carry solder balls, allowing the carrier to be reflow soldered to the primary circuit board.
While such CSPs maintain a small overall size, they are not without potential disadvantages. For example, the overall electrical impedance between the die's signal points and corresponding connections on the primary circuit board can be undesirably high, contributing to signal degradation and limiting upper operating frequencies. Also, such CSPs may offer poor thermal conduction between the die and the primary circuit board, thus limiting the amount of power that may be dissipated in the die.
BRIEF SUMMARY OF THE INVENTION
A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier. The carrier provides for electrical interconnection with the die and is suitable for mounting on a primary circuit board. Wire bond fingers on the top of the carrier are arrayed around the die mounting area and provide connection points for the die's bond wires, which points are generally grouped in rows along each edge of the carrier. A ground plane surrounds these groups of connection points and also covers the die mounting area. Thermal vias in the die mounting area electrically and thermally couple the ground plane to a second ground plane on the bottom of the carrier. That ground plane includes ground pads with attached solder balls for connection with the primary circuit board. Similarly, signal vias couple the wire bond fingers to corresponding signal pads on the bottom of the carrier, the pads of which also carry solder balls for attachment to the primary circuit board.
By providing a top-side ground plane covering the die mounting area, die grounding is accomplished through mounting the die in electrical connection with the ground plane. This eliminates the need for using one or more bond wire connections to ground the die. Thus, all bond wires may be dedicated to signal connections. Surrounding the bond wire finger terminations for all of these signal connections with the top-side ground plane enhances signal integrity by minimizing cross-talk and ground loop area. Further, positioning thermal vias in the top-side ground plane generally within the die mounting area provides low thermal and electrical impedance connections between the top and bottom side ground planes. The ground pads with attached solder balls on the bottom side ground plane complete the low thermal and electrical impedance connections between the die and the primary circuit board.


REFERENCES:
patent: 5468999 (1995-11-01), Lin et al.
patent: 6380633 (2002-04-01), Tsai
patent: 2002/0185734 (2002-12-01), Zhao et al.
patent: WO 98/48449 (1998-10-01), None

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