Boots – shoes – and leggings
Patent
1994-01-07
1997-05-13
Swann, Tod R.
Boots, shoes, and leggings
395500, 395 60, 395853, 395460, 395457, 364DIG1, G06F 1202
Patent
active
056300972
ABSTRACT:
A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The primary feature of the invention is to add bus activity sampling logic to the CPU and enhance the operating system to allow the operating system to detect when cache thrashing is occurring and remap data pages to new physical memory locations to eliminate the cache thrashing situation.
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Abramson Kenneth D.
Butts, Jr. H. Bruce
Orbits David A.
Digital Equipment Corporation
Fisher Arthur W.
Maloney Denis G.
Peikari J.
Swann Tod R.
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