Enhanced branch delay slot handling with single exception progra

Details Enhanced branch delay slot handling with single exception progra Enhanced branch delay slot handling with single exception progra

1995-12-06

1998-06-30

Kim, Kenneth S.

395570, 395591, 39580041, G06F 938

Patent

active

057747091

ABSTRACT:
The handling of branch delay slots in MIPS microprocessors is enhanced. Branch instructions can be placed in branch delay slots by the judicious operation of the Exception Pointer Counter and the BD bit in the Cause register for exception handling.

REFERENCES:
patent: 4755966 (1988-07-01), Lee et al.
patent: 4868735 (1989-09-01), Moller et al.
patent: 5481685 (1996-01-01), Nguyen et al.
patent: 5564028 (1996-10-01), Swoboda et al.
patent: 5603047 (1997-02-01), Caulk, Jr.

Affiliated with

Also associated with

Rating

Enhanced branch delay slot handling with single exception progra does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced branch delay slot handling with single exception progra, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced branch delay slot handling with single exception progra will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1870556