Enhanced blank check erase verify reference voltage source

Details Enhanced blank check erase verify reference voltage source Enhanced blank check erase verify reference voltage source

1998-01-23

1999-04-27

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518523, 36518529, 327530, 327538, 327543, G11C 1606

Patent

active

058986189

ABSTRACT:
A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.

REFERENCES:
patent: 5561631 (1996-10-01), Curd
patent: 5650672 (1997-07-01), Curd
patent: 5661685 (1997-08-01), Lee et al.
"The Programmable Logic Data Book", 7/1996, published by Xilinx Inc., 2100 Logic Drive, San Josee, CA, 95124, pp. 3-71 to 3-78.

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