Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-05-22
2004-08-31
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06785702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an energy saving multiplication device and its method. More particularly, the invention relates to a Booth multiplication device that can lower power consumption and a method that uses the Booth multiplication device to lower power consumption.
2. Related Art
Along with the development in semiconductor manufacturing processes, digital signal processors (DSPs) and application specific integrated circuits (ASICs) adopt the energy saving system designs to satisfy the need in the portable device market. In the commonly seen complementary metal-oxide semiconductor (CMOS) circuits, the main power consumption is due to the charging and discharging of terminal capacitors when the transistor is under transition.
The multiplier in systems such as the digital filter and the DSP is a basic and important element and one of the crucial factors, that determines the system operating speed. However, the power consumption of the multiplier in a chip is relatively larger than other elements. As the DSP and the ASIC have more functions and are operating at higher frequencies, the extensive uses of the multiplier will result in immense power consumption.
The conventional 2's complement high speed multiplier can adopt the Booth algorithm to process the multiplicand and the multiplier and to generate partial products. A counter or compressor array with the Wallace-tree structure then performs addition operations on the partial products and outputs the multiplication result.
Referring to
FIG. 1
, in the Booth multiplier
100
the input multiplicand
110
a
and the multiplier
110
b
are received and transmitted by registers
102
a
,
102
b
, respectively, encoded/decoded by a Booth encoder/decoder
104
, and processed to generate and output partial products
112
. The partial products
112
are added by a counter
106
and a carry look-ahead adder (CLA)
108
then performs accumulation to obtain the product
114
of the multiplicand
110
a
and the multiplier
110
b
. From the operation mode of the conventional Booth multiplier one can learn that after completing Booth encoding/decoding, a huge amount of addition operations have to be performed and the addition operations will result in switching activities in the circuit.
The above-mentioned switching activities in the circuit due to additions are the reason for main power consumption in the conventional Booth multiplier. Thus, how to decrease the power consumption of a multiplier has become an important subject nowadays. The U.S. Pat. No. 6,021,424 discloses a multiplier with a lower-power, high-efficiency input circuit. By controlling the time and order of the input data, the data input are synchronous to decrease unnecessary power consumption. The U.S. Pat. No. 6,029,187 discloses another high-speed multiplier structure that can increase the operation speed and maintain the regularity of the multiplier structure. It improves the addition structure and method in the adder to balance the delay of data transmission and to decrease unnecessary power consumption.
“The low power multiplier disclosed in the U.S. Pat. No. 5,818,743 controls pulse signals to synchronously input the partial products for performing addition operations, thus decreasing the interior power consumption. The U.S. Pat. No. 5,787,029 proposes an extremely low power multiplier that decreases power consumption by improving the Booth encoder/decoder so that the decoded partial products change the subsequent addition operations. The U.S. Pat. No. 5,485,413 uses a multiplier using the Booth algorithm that can manipulate the sign extension in the multiplication operation to decrease the addition structure for the sign extension in partial products and to decrease the hardware structure complexity and power consumption.”
Furthermore, the low power parallel multiplier disclosed in the U.S. Pat. No. 4,982,355 synchronizes the data output from each level to save power consumption. The U.S. Pat. No. 4,972,362 proposes a binary multiplier using the Booth multiplication algorithm and its method. It uses a Booth carry save adder (CSA) to process data using pipelines so that the internal pulse is synchronized with the system pulse. In these U.S. patents, the method to save power consumption can be categorized into three types: (1) modify the structure of the Booth encoder/decoder to lower the power consumption thereof and to change subsequent additions; (2) control to synchronize the data input to each level to decrease unnecessary internal power consumption; (3) save unnecessary addition structures in the sign extension of data. Nevertheless, these conventional techniques do not take in to account the influence of the dynamic range sizes of input data on the system power consumption.
SUMMARY OF THE INVENTION
In view of the foregoing, the switching activities due to addition operations on the partial products are the sources of main power consumption in currently widely used Booth multiplier. Therefore, the present invention provides a low power multiplication structure which can decrease the times of switching activities in the circuit to lower the power consumption and can be applied to a usual high-speed multiplier. It is then an object of the invention to provide a low power consuming multiplication device, which uses a dynamic range determination (DRD) unit to perform exchange actions of large and small dynamic-range numbers among input data. That is, the input datum with a smaller dynamic range is taken as a multiplier to perform Booth encoding/decoding. The power consumption is then decreased by increasing invalid partial products, thus decreasing the transition probabilities of the functional blocks after the Booth encoding/decoding unit.
It is another object of the invention to provide a multiplication method, which compares the numerical values to be multiplied together and chooses the smaller one (the one with a smaller dynamic range) to perform Booth encoding/decoding. Since the most-significant bits of the smaller dynamic-range one are a series of “0”s or “1”s, the numerical values of the partial products generated after the Booth encoding/decoding for the most-significant bits will be 0. The partial products are then shifted and accumulated to obtain the product of input numerical values.
Pursuant to the above-mentioned and other objects, the present invention provides a multiplication device comprising a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit and uses the input value with a smaller dynamic range as the multiplier to perform Booth encoding and then to perform Booth decoding with the other input value with a larger dynamic range to output partial products. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the product of the input data.
Furthermore, the present invention provides a Booth multiplication device, which includes an input master latch, a dynamic range determination unit, a transition control slave latch, a Booth encoding/decoding unit, a counter array and a carry look-ahead adder (CLA). The input master latch receives and transmits the numerical values to be multiplied together. The dynamic range determination unit couples to the input master latch to determine the dynamic ranges of the input numerical values and to pass or exchange data flows according to their dynamic-range size relation. The transition control slave latch couples to the dynamic range determination unit to receive and transmit numerical value segments with larger and smaller dynamic ranges. The Booth encoding/decoding unit couples to the transition control slave latch to take the numerical value segment with a smaller dynamic ra
Chen Kuo-Hua
Chen Oscal T.-C.
Ma Ruey-Liang
Industrial Technology Research Institute
Mai Tan V.
Sughrue & Mion, PLLC
LandOfFree
Energy saving multiplication device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Energy saving multiplication device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Energy saving multiplication device and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3351759