End of packet detector and resynchronizer for serial data buses

Details End of packet detector and resynchronizer for serial data buses End of packet detector and resynchronizer for serial data buses

1993-03-04

1995-03-21

Marcelo, Melvin

Multiplex communications

Wide area network

Packet switching

370108, 375118, H04L 704

Patent

active

054003407

ABSTRACT:
An interface device for a point-to-point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmissions of packets of data, includes a low latency resynchronizing circuit and an end of packet detector which is independent of control data within the packet. The resynchronizer is based on an interface which receives bus data and bus clock from a transmission of a packet on the bus. A circular input buffer stores bus data received from the bus in data locations indicated by an input pointer in response to the bus clock. An input pointer generator supplies the input pointers to the input buffer in a circular sequence, beginning in a particular location during a first bus clock in a packet. An output selector supplies bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer and in response to the local clock. An output pointer generator supplies the output pointer in a circular sequence beginning in the particular location in a local clock cycle after the first bus clock in the packet. The end of packet is detected using a comparator coupled to the input pointer generator and the output pointer generator. When the input pointer and the output pointer match, the end of the data packet is indicated. The overrun only occurs after the bus clock has stopped at the end of the packet which stops the output pointer generator.

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