Encryption key generation circuit

Cryptography – Key management – Having particular key generator

Reexamination Certificate

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Reexamination Certificate

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07039186

ABSTRACT:
An encryption key generation circuit for generating at least one 128-bit round sub key used in at least one sub round for encryption of 128-bit plaintext, from an encryption key having 64×n bits (2≦n≦4; where n is an integer) includes a byte rotation circuit for performing byte rotation of rotating (8×n+1)-byte information by 1 byte; a 3-bit rotation circuit for performing 3-bit rotation of rotating bits in each byte of the (8×n+1) -byte information by 3 bits; and 16 adders for adding a 128-bit bias value to (8×n)-byte information from the byte lowest of the (8×n+1)-byte information processed with the byte rotation and the 3-bit rotation, so as to generate one of the at least one 128-bit round sub key in each sub round.

REFERENCES:
patent: 6314186 (2001-11-01), Lee et al.
patent: 0 443 752 A2 (1991-08-01), None
patent: 11-45049 (1999-02-01), None
patent: 11-45049 (1999-02-01), None
patent: 2000-39840 (2000-02-01), None
Cyllnk Corporation, SAFER+, First Advanced Encryption Standard Candidate Conference,□□Aug. 20-22, 1998; Ventura, CA; slides 12 and 13□□.
Cylink Corporation, SAFER+, First Advanced Encryption Standard Candidate Conference, Aug. 20-22, 1998, Ventura, CA.
Charles S. Williams, Comments on Cylink's AES Candidate Algorithm SAFER+, Apr. 14, 1999, pp. 1-7, XP-002226944.

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