Encryption circuit

Details Encryption circuit Encryption circuit

2007-01-02

2007-01-02

Moazzami, Nasser (Department: 2136)

Cryptography

Communication system using cryptography

Time segment interchange

Reexamination Certificate

active

10034321

ABSTRACT:
An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher. A round processing unit comprises: a first Round Key Addition circuit that adds a round key value to input data; an intermediate register/Shift Row transformation circuit that temporarily stores the output of the first Round Key Addition circuit and executes Shift Row transformation; a Byte Sub transformation circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which executes Byte Sub transformation; a second Round Key Addition circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which adds round key values; a Mix Column transformation circuit that executes Mix Column transformation upon the outputs of the second Round Key Addition circuit; and a second selector that outputs to the second Round Key Addition circuit one of the outputs of a first selector, the intermediate register/Shift Row transformation circuit, the Byte Sub transformation circuit, and the Mix Column transformation circuit.

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Henry Kuo, et al., “Architectural Optimization for a 1.82Gbits/see VLSI Implementation of the AES Rijndael Algorithm”, Electrical Engineering Department, University of California, Los Angeles.
Máire McLoone, et al., “High Performance Single-Chip FPGA Rijndael Algorithm Implementations”, DiSip™ Laboratories, School of Electrical and Electronic Engineering, The Queen's University of Belfast, Belfast BT9 5AH, Northern Ireland.
Viktor Fischer, et al., “Two Methods of Rijndael Implementation in Reconfigurable Hardware”, Laboratoire Traitement du Signal et Instrumentation, Unite Mixte de Recherche CNRS 5516, Université Jean Monnet, Sainte-Etienne, France.
Joan Daemen, et al., “AES Proposal: Rijndael”, The Rijndael Block Cipher. http://csrc.nist.gov/encryption/aes/rijindael/Rijindael.pdf.
M. McLoone et al., “High Performance Single-Chip FPGA Rijndael Algorithm Implementations”, Cryptographic Hardware and Embedded Systems, 3rdInternational Workshop, Ches 2001, Paris, France, May 14-16, 2001, Proceedings, Lecture Notes in Computer Science, Berlin: Springer, DE, vol. 2162, May 14, 2001, pp. 65-76.
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