Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-09-16
2001-07-03
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S506000
Reexamination Certificate
active
06255711
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuits and fabrication techniques for electrically isolating the various components in an integrated circuit. More particularly, the present invention relates to integrated circuits and fabrication techniques that electrically isolate the various components by an isolation process known as LOCOS, which stands for localized oxidation of silicon.
BACKGROUND OF THE INVENTION
Microelectronic circuitry in the form of integrated circuits have utilized the deposition of films of silicon dioxide and silicon nitride as insulator or dielectric layers to electrically isolate independent circuit portions. Junction isolation utilizing by example, N-type material diffusion, N-type epitaxial layer deposition and P-type doping is a known scheme for electrically isolating P-type semiconductor material from N-type semiconductor material in an integrated circuit substrate structure. Other electrical isolation schemes include dielectric isolation whereby trenches are formed for receiving an oxide layer, a polysilicon material and for delineating silicon pockets on an opposing side. After processing, the oxide electrically separates the silicon pockets from the polysilicon layer. The junction and dielectric isolation processes require substantial surface area and have resulted in an alternative process termed LOCOS which conserves on the use of the surface area by selectively oxidizing patterns on a silicon substrate. A problem associated with the LOCOS isolation technique is the oxide encroachment of the silicon dioxide that results under the silicon nitride layer, see
FIG. 7.0
. The oxide encroachment is known in the industry as a bird's beak. The length of the beak relates to mechanical stress in the silicon which impacts the performance of circuits formed in that area. Solutions to minimize the stress problem include formation of a pad oxide under the silicon nitride and controlling the oxidation temperature and width of the active device. Other known processes include a variation of the LOCOS process which is known in the industry as SWAMI, as developed by Hewlett Packard. The SWAMI process includes outwardly etching the silicon nitride and the pad oxides at 60 degrees such that the subsequent oxidation and beak formation length is limited. Other methods include using high-pressure oxidation techniques where the oxidation is grown faster and at a lower temperature which results in minimizing the growth of the bird's beak.
The foregoing processes for minimizing the length of the bird's beak in LOCOS isolation are not deemed adequate for integrated circuit technologies in the sub-0.25 &mgr;m range. In this sub-micron range, the length of the bird's beak must be less than 0.1 &mgr;m to avoid formation of junction capacitance which results in leakage current paths. By example, computer memory products, such as flash memory using high density, sub-micron, single transistor cell MOS design, require isolation between cells that maintain their integrity throughout the life of the product. To applicant's knowledge, the use of fabricated silicon nitride spacers, in combination with pad oxide and silicon nitride layers has not been used to produce LOCOS isolation. The silicon nitride spacer surrounding the active part of the device prevents growth of oxide and thus prevents dislocation loops from forming in the MOS gate area which results in an encroachless LOCOS form of isolation. Further, this form of LOCOS isolation does not require a polishing process, which can cause gate oxide damage and formation of undesirable current leakage paths in subsequently formed microelectronic devices.
Thus, a primary object of the present invention is to provide a microelectronic integrated circuit substrate having LOCOS isolation structure whose oxidation encroachment region is substantially less than 0.1 &mgr;m.
A related object is to provide a fabrication process for producing a microelectronic integrated circuit substrate having LOCOS isolation structure in accordance with the foregoing primary object.
A specific object of the present invention is to provide a microelectronic integrated circuit substrate having fabrication structure comprising silicon nitride spacers for producing a LOCOS isolation structure whose oxidation encroachment region is substantially less than 0.1 &mgr;m.
Another related object is to provide a fabrication process for producing a microelectronic integrated circuit substrate having LOCOS isolation structure in accordance with the foregoing specific object.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the foregoing objects are accomplished by providing a fabrication process for fabricating an integrated circuit substrate structure having LOCOS isolation areas formed such that the oxidation encroachment at a surface region patterned on a surface of the substrate is less than 0.1 &mgr;m. The process comprises deposition steps for forming a 0.75 &mgr;m. to 1.0 &mgr;m layer of silicon dioxide (SiO
2
) over thin layers of silicon dioxide (0.01 &mgr;m. to 0.05 &mgr;m) and silicon nitride (0.05 &mgr;m. to 0.10 &mgr;m) over a surface region of the substrate, which may be used for fabricating a microelectronic circuit element, such as a MOS transistor. Adjacent the forgoing stack of passivation layers, silicon nitride spacers are formed to effectively widen the protected surface region where a circuit element may be formed. The silicon nitride spacer formed limits the growth of oxide into the active surface region. The resulting structure, after removal of the silicon nitride, is one having an oxide encroachment region, comprising silicon dioxide, that is less than 0.1 &mgr;m. The resulting encroachment region, is best described as being less than 0.1 &mgr;m at a surface level of said surface region and having a slight bowing formation of silicon dioxide into the body of the silicon substrate material. The encroachment region is preferably not characterized as a bird's beak.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 4583281 (1986-04-01), Ghezzo et al.
patent: 4868136 (1989-09-01), Ravaglia
patent: 5712186 (1998-01-01), Thakur
patent: 5726091 (1998-03-01), Tsai et al.
patent: 5863817 (1999-10-01), Chu et al.
patent: 5891788 (1999-04-01), Fazan et al.
patent: 5930649 (1999-07-01), Park
Stanley Wolf, Silicon Processing for the VSLI Era, vol. 1, Lattice Press, p. 36 (1990).
Stanley Wolf, Silicon Processing for the VSLI Era, vol. II, Lattice Press, p. 38 (1990).
Stanley Wolf, Silicon Processing for the VSLI Era, vol. III, Lattice Press, p. 363 (1995).
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Loke Steven
Owens Douglas W.
LandOfFree
Encroachless LOCOS isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Encroachless LOCOS isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Encroachless LOCOS isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2550697