Multiplex communications – Wide area network – Packet switching
Patent
1986-03-17
1989-01-10
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370112, 358 11, H04J 300, H04J 304, H04N 1120
Patent
active
047978830
ABSTRACT:
A circuit includes shift registers (SR1, SR2, SR3) having different write and read rates under the control of clock pulses of different frequencies so that they form part of a signal compression or signal expansion circuit for encoding from simultaneous signals to the time division multiplex signal and for decoding from the time division multiplex signal to the simultaneous signals, respectively. The circuit is an integrated circuit (IC) having shift registers (SR1, SR2, SR3) suitable for both series-in, parallel-out and parallel-in, series-out operation. The shift register (SR1) with the greatest number of register stages is coupled to parallel connections of at least two further shift registers (SR2, SR3) via a through-connection circuit SC1 for a parallel bi-directional connection of the register stages. The series inputs and series outputs of at least the three shift registers are each coupled to a connection terminal of the integrated circuit (IC).
REFERENCES:
patent: 4264954 (1981-04-01), Briggs et al.
patent: 4316061 (1982-02-01), Ahamed
patent: 4320501 (1982-03-01), LeDieu et al.
patent: 4593390 (1986-06-01), Hildebrand et al.
Gadson Gregory P.
Goodman Edward W.
Olms Douglas W.
Scutch III Frank M.
U.S. Philips Corporation
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