Encoding method and apparatus therefor, and optical-disk...

Dynamic information storage or retrieval – Binary pulse train information signal – Having specific code or form generation or regeneration...

Reexamination Certificate

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C369S059130, C341S059000

Reexamination Certificate

active

06807137

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a channel coding and particularly relates to an improved method and an apparatus for encoding binary data in such a way that the low-frequency component of encoded data is suppressed. The present invention further relates to an optical-disk recording method and an apparatus therefor.
2. Description of the Related Art
For many data-transmission systems and data-recording systems, suppression of low-frequency components in encoded data is important is essential for aiding a decoder in reproducing original data in a noisy environment and avoiding cross coupling with the components of other systems, such as a servo system.
A common strategy used for achieving such a spectral-constraint encoding is to add redundant information to a data word for performing the encoding such that the data word can be equivalently encoded into at least two substitution-information data signals. By selecting substitution information offering a low DC-component, a low-frequency spectrum of the encoded data can be effectively suppressed.
However, the quality of the low-frequency component suppression depends greatly on the amount of the redundant information used for achieving the DC-component suppression and a strategy for selecting a predetermined substitution-encoder mapping method from among a plurality of substitution-encoder mapping methods. Where the amount of the redundant information increases, the quality of the DC-component suppression improves and the encoding efficiency decreases. Therefore, it is important to select an effective strategy for selecting the predetermined substitution-encoder mapping method for designing a system that adds constraints on the DC component of encoded data and that maintains high encoding efficiency at low cost.
This document illustrates a method for improving the selection strategy commonly used for encoders and an apparatus therefor. Accordingly, it becomes possible to improve the quality of DC-component suppression without decreasing the encoding efficiency.
Hitherto, a plurality of methods has been introduced for adding redundant bit data to encoded data so as to suppress the DC component of the encoded data.
For example, in an 8/14 modulation (EFM) encoding method used for a compact-disk (CD) system, an 8-bit data-to-14-bit data translation table maps a sequence of data bytes to code words. The generated translation table satisfies a minimum run-length constraint and ensures that two binary “1” symbols during the encoding process are separated by at least two binary symbols “0” and that a maximum run-length constraint ensures that no binary sequence including ten successive “0” symbols or more occurs in the encoded data.
The minimum run-length constraint depends on the smallest feature size of the physical pit structure of a CD. The maximum run-length constraint is necessary for reliable clock reproduction during decoding process.
A sequence of three margin bits is inserted between each pair of code words. The values of the margin bits can be freely determined as long as the above-described run-length constraints are satisfied.
The freedom of determining the values of the margin bits is limited for the DC-component suppression. After selecting the margin bits, the run-length-encoded data including the margin bits are NRZI (non-return to zero inverse) modulated, so that each “1” symbol in the encoded data bit sequence is mapped to a bit transition in the modulation bit sequence.
For determining the values of the margin bits so that DC components are reduced, a running digital sum (RDS) value is determined to be the difference between the number of binary “1” symbols and the number of binary “0” symbols over the modulation bit sequence. The data to be encoded are presented to the encoder as 8-bit words in a sequential order. For each data word to be encoded, the margin bits are selected such that the RDS value approaches zero as much as possible and the number of “1” symbols and the number of “0” symbols in the modulation bit sequence are balanced.
Another example for using redundant information for reducing a DC component is an EFM
+
encoding method used for a digital versatile disk (DVD) system. The EFM
+
encoding method is an improved modification of the EFM encoding method. In the EFM
+
encoding method, a data word of 8 bits is mapped to a code by using an 8 bit-to-16 bit state-dependent translation table.
Unlike the EFM encoding method, according to the EFM
+
encoding method, there are no margin bits used for the DC-component control and code word concatenation. However, each data word can be encoded in another way by using a substitution table.
However, the selection strategy of the EFM
+
encoding method for the DC-component suppression is essentially the same as that used in the EFM encoding method for each valid encoding substitution information, wherein an RDS value closest to zero is selected.
A third example of the DC-free encoding method is an 8/14 modulation parity preserving (EFMPP) encoding method proposed by Philips Corporation. According to this EFMPP encoding method, a data word of 8 bits is mapped to a code by using an 8/15 mapping table, as in the case of the EFM
+
encoding. Since the EFMPP encoding method is unique and not used in general, there is nothing to show a substitution code for a data word. For achieving the DC-component control, the data bit sequence is therefore interleaved with a DC control bit sequence before the encoding is actually performed. Accordingly, the redundancy required for suppressing the DC component is provided.
Both the EFM encoding method and the EFM
+
encoding method use the same strategy, that is to say, the RDS value is calculated for calculating the value of a DC-control bit. Further, the RDS value closest to zero is selected.
As has been described above, the inventors of the present invention conclude that there are different techniques for adding redundant information to encoded data, such as:
(1) Adding redundant information to a modulation bit sequence by using margin bits or substitution-encoder mapping, and
(2) Adding redundant information by inserting control bits into a bit data sequence before encoding.
However, in a particular encoding method such as the EFM encoding method, a DC-component suppression algorithm and an encoding translation method are tightly and architecturally integrated, and the DC-component suppression method and the encoding translation are conceptually separated from each other.
Therefore, the present invention does not depend on a particular encoding method such as the EFM encoding method used for the CD system or the EFM
+
encoding method used for the DVD system. Rather, the present invention allows the encoder to select data for code mapping so as to achieve the DC-component suppression. By implementing a novel selection strategy for selecting substitution data for the code mapping, the low-frequency component of encoded data is suppressed.
In the above-described encoding methods, both the transition from the EFM encoding method to the EFM
+
encoding method and the transition from the EFM
+
encoding method to the EFMPP encoding method achieve high encoding efficiency. However, this high encoding efficiency is obtained at the sacrifice of the quality of the DC-component suppression. Therefore, there is a need for a better DC selection strategy that does not decrease the encoding efficiency.
Another example DC-free encoding method is the EFM combi-code (EFMCC) encoding method proposed by Philips Corporation. In the EFMCC method encoding, a data word of 8 bits is mapped to a code mostly by using an 8-to-15 main-code mapping method similar to that of the EFM
+
encoding method. However, at predetermined word intervals, 8-to-17 substitution-code mapping is performed, which offers a choice between two code words. A subsequent state in a finite state machine (FSM) of one of these two code words is the same as that of the other.

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