Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2001-03-22
2004-07-20
Kelly, Chris (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C375S240160, C370S536000, C370S537000, C345S003100
Reexamination Certificate
active
06765961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to encoding devices, and more particularly to encoding devices allowing multiplexing of a video signal and an audio signal according to a predetermined compression encoding standard.
2. Description of the Background Art
Recently, MPEG2 (Moving Picture Experts Group) has become widely adopted as an international standard of data compression encoding in various applications including digital satellite broadcasting and DVD (Digital Versatile Disc). MPEG2 standard, defined in three layers, that is, video, audio and system layers, allows multiplexing of a video signal and an audio signal.
In general, according to MPEG2 standard, audio data compression and a process relating to a system do not require an excessively enormous and complicated operation, whereas an operation for video data compression is complicated and the amount of operation is enormous.
In a multiplexing of an audio signal and a video signal according to the conventional MPEG2 standard, generally the process relating to the audio and the system is realized through a software process in a processor unit, whereas the process relating to video is realized through a dedicated hardware, which is controlled through a software process in the processor unit.
Encoding devices performing such multiplexing are, therefore, implemented as multiplexing encoding systems formed as a combination of three devices, that is, an audio compression encoding device and a system multiplexing device both realized with a DSP (Digital Signal Processor), for example, in a software-like manner, and a video compression encoding device including an LSI (Large Scale Integrated Circuit) dedicated for image compression and a processor unit controlling the LSI.
With reference to
FIG. 12
, a multiplexing encoding system
300
of the conventional art includes a video compression encoding device
400
performing a video encoding process on a video signal, an audio compression encoding device
500
performing an audio encoding process on an audio signal and a system multiplexing device
600
performing a system process for multiplexing encoded video data and encoded audio data.
Video compression encoding device
400
performs a compression encoding of original video data supplied to a video input terminal
402
to generate encoded video data. Audio compression encoding device
500
performs a compression encoding of original audio data supplied to an audio input terminal
502
to generate encoded audio data.
System multiplexing device
600
receives encoded video data and encoded audio data from video compression encoding device
400
and audio compression encoding device
500
, respectively, performs a multiplexing process according to a format defined by a system layer of MPEG2 standard, for example, generates and outputs resulting compressed data via an output terminal
606
. The compression encoding process will also be referred to as an encoding process hereinbelow.
With reference to
FIG. 13
, video compression encoding device
400
includes a video encoding unit
420
encoding original video data supplied to video input terminal
402
, a processor unit
410
controlling the encoding process at video encoding unit
420
, an FIFO (First In First Out) buffer
455
receiving encoded video data generated in video encoding unit
420
, a video timing generation unit
430
generating a timing signal for controlling a timing of execution of the video encoding process and an internal bus
450
. The encoded video data supplied to FIFO buffer
455
is output via a video output terminal
406
. Processor unit
410
is connected to video encoding unit
420
via internal bus
450
. As video encoding unit
420
, an image compression LSI, which is a dedicated hardware, is employed, for example.
Video encoding unit
420
includes a register
422
to hold a control parameter employed in the video encoding process. The control parameter held by register
422
is set through processor unit
410
via internal bus
450
. The timing signals generated from video timing generation unit
430
include a picture timing signal PSYNC indicating an activation timing of a picture-related process and a macro block timing signal MBSYNC indicating an activation timing of a macro block-related process (hereinafter referred to also as MB process) in MPEG2 standard, for example.
FIG. 14
shows a timing chart referenced for describing an execution timing of the video encoding process.
With reference to
FIG. 14
, the picture-related process is executed in response to the generation of picture timing signal PSYNC and the MB process is executed in response to the generation of macro block timing signal MBSYNC.
In the video compression encoding, the number of frames n (n is a natural number) included in a second is determined and a cycle of the generation of picture timing signal PSYNC is 1
second. For example, when thirty frames are included in a second, the cycle of picture timing signal PSYNC is 1/30 second.
In MPEG2 standard, the video compression encoding is executed with a one-frame image divided into macro blocks (hereinafter referred to simply as MB) serving as a unit of processing, of sixteen pixels×sixteen lines. If an image of one frame is formed from 720 pixels in a vertical direction×480 lines in a horizontal direction, one frame includes 1350 MB's. Then, video timing generation unit
430
generates 1350 macro block timing signals MBSYNC during one cycle of picture timing signal PSYNC.
Video encoding section
420
operates in response to timing signals PSYNC and MBSYNC. In particular, video encoding unit
420
executes the MB process for each MB in response to macro block timing signal MBSYNC and executes the picture-related process which is common to all MB included in one frame in response to picture timing signal PSYNC.
A necessary control parameter for the picture-related process and the macro block-related process is set in register
422
through processor unit
410
. Processor unit
410
, hence, must operate in synchronization with timing signals PSYNC and MBSYNC.
When these timing signals PSYNC and MBSYNC generated from video timing generation unit
430
are supplied to an interrupt terminal of processor unit
410
, processor unit
410
can execute an operation corresponding to the picture-related process and the macro block-related process as an interrupt process in synchronization with video encoding unit
420
.
With reference to
FIG. 15
, audio compression encoding device
500
includes an FIFO buffer
532
receiving original audio data supplied to audio input terminal
502
, a processor unit
510
including a software for executing an encoding process on the original audio data, an FIFO buffer
534
receiving encoded audio data supplied from processor unit
510
, an audio output terminal
505
supplying the encoded audio data supplied from FIFO buffer
534
, and an internal bus
550
. Processor unit
510
is connected to FIFO buffers
532
and
534
via internal bus
550
.
The original audio data supplied to audio input terminal
502
is then supplied to FIFO buffer
532
. Processor unit
510
reads the original audio data from FIFO buffer
532
via internal bus
550
. Processor unit
510
encodes the read original audio data according to an internally stored program to generate encoded audio data. The encoded audio data is written into FIFO buffer
534
via internal bus
550
.
The encoded audio data supplied to FIFO buffer
534
is output from audio output terminal
505
. The activation of the program for executing the audio encoding process in processor unit
510
is controlled through an audio timing generation unit
520
.
With reference to
FIG. 16
, the audio encoding process in processor unit
510
is activated in response to generation of a timing signal FSYNC. When a sampling frequency of 48 kHz according to a layer II of the MPEG1 audio standard is employed as a mode for the audio encoding process, a frame defined by 1152 samples will be processed as one
Kumaki Satoshi
Segawa Hiroshi
Kelly Chris
McDermott Will & Emery LLP
Renesas Technology Corp.
Wong Allen
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