Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2003-05-02
2004-07-20
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
C341S061000
Reexamination Certificate
active
06765507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to encoding devices and methods for performing serially concatenated convolutional coding or serial concatenated trellis coded modulation and to decoding devices and methods for decoding codes generated by serially concatenated convolutional coding or serial concatenated trellis coded modulation performed by such encoding devices and methods.
2. Description of the Related Art
Nowadays, a considerable amount of research is being conducted in communications fields, such as mobile communications and deep space communications, and in broadcasting fields, such as terrestrial and satellite digital broadcasting. In relation to such research, coding theory research has been extensively conducted to improve the efficiency of error-correcting coding and decoding.
One known theoretical limit of code performance is the Shannon limit, which is given by Shannon's channel coding theorem.
The purpose of coding theory research is to develop codes that have near-Shannon-limit performance. Recently, for example, serially concatenated convolutional codes (hereinafter referred to as SCCC) have been developed by an encoding method that generates codes showing performance near the Shannon limit.
SCCC coding is performed by serially concatenating two convolutional encoders and an interleaver. SCCC decoding is performed by serially concatenating two soft-output decoder circuits, which exchange information with each other to obtain a final decoded result.
One known application of SCCC coding is serial concatenated trellis coded modulation (hereinafter referred to as SCTCM), which is described in D. Divsalar and F. Pollara, “Serial and Hybrid Concatenation Codes with Applications”, in Proc. Int. Symp. on Turbo Codes and Related Topics, Brest, France, pp. 80-87, September 1997. SCTCM combines SCCC coding and multi-level modulation and takes into consideration the entirety of the signal constellation of modulated signals and the decoding characteristics of error-correcting codes.
Specific examples of an encoding device that performs SCTCM coding and a decoding device that performs decoding of a code in SCTCM will now be described. In the following description, as shown in
FIG. 13
, digital information is encoded by an encoding device
201
included in a transmitter (not shown). The output of the encoder
201
is input to a receiver (not shown) via a memoryless channel
202
and decoded by a decoding device
203
included in the receiver. The decoded information is then observed.
The encoding device
201
that performs SCTCM coding includes, for example, as shown in
FIG. 14
, a convolutional encoder
210
that encodes an outer code, an interleaver
220
that permutes input data, a convolutional encoder
230
that encodes an inner code, and a multi-level modulation mapping circuit
240
that performs signal point mapping based on a predetermined modulation system. The encoding device
201
performs a serially concatenated convolutional operation on 2-bit input data D
201
with a code rate of 2/3 to convert the input data D
201
into 3-bit encoded data D
204
, maps the encoded data D
204
to a transmission symbol in, for example, eight-phase shift keying (hereinafter referred to as 8PSK), and outputs a resultant 3-bit encoded transmission symbol D
205
.
Referring to
FIG. 15
, the convolutional encoder
210
has three exclusive OR circuits
211
,
213
, and
215
and two shift registers
212
and
214
.
The exclusive OR circuit
211
computes the exclusive OR of 2-bit input data D
201
1
and D
202
2
and supplies the computation result to the shift register
212
.
The shift register
212
continuously supplies 1-bit data maintained therein to the exclusive OR circuit
213
. In synchronization with a clock signal, the shift register
212
maintains new 1-bit data supplied from the exclusive OR circuit
211
and supplies the new data to the exclusive OR circuit
213
.
The exclusive OR circuit
213
computes the exclusive OR of data supplied from the shift register
212
and the 1-bit input data D
201
1
of the 2-bit input data D
201
and supplies the computation result to the shift register
214
.
The shift register
214
continuously supplies 1-bit data maintained therein to the exclusive OR circuit
215
. In synchronization with a clock signal, the shift register
214
maintains new 1-bit data supplied from the exclusive OR circuit
213
and supplies the new data to the exclusive OR circuit
215
.
The exclusive OR circuit
215
computes the exclusive OR of data supplied from the shift register
214
and the input data D
201
1
and D
201
2
and supplies the computation result serving as 1-bit encoded data D
202
3
of 3-bit encoded data D
202
to the interleaver
220
at a subsequent stage.
When the convolutional encoder
210
described above receives the 2-bit input data D
201
1
and D
202
2
, the convolutional encoder
210
performs a convolutional operation of the input data D
201
1
and D
202
2
and outputs the operation result as 3-bit encoded data D
202
1
, D
202
2
, and D
202
3
to the interleaver
220
at the subsequent stage. In other words, the convolutional encoder
210
performs a convolutional operation to encode the outer code with a code rate of 2/3 and outputs the generated encoded data D
202
to the interleaver
220
at the subsequent stage.
The interleaver
220
interleaves the encoded data D
202
consisting of a 3-bit sequence output from the convolutional encoder
210
and outputs interleaved data D
203
consisting of the generated 3-bit sequence to the convolutional encoder
230
at a subsequent stage.
Referring to
FIG. 16
, the convolutional encoder
230
includes an exclusive OR circuit
231
and a shift register
232
.
The exclusive OR circuit .
231
computes the exclusive OR of 3-bit interleaved data D
203
1
, D
203
2
, and D
203
3
. The exclusive OR circuit
231
outputs the computation result serving as 1-bit encoded data D
204
3
of 3-bit encoded data D
204
to the multi-level modulation mapping circuit
240
at a subsequent stage and supplies the computation result to the shift register
232
.
The shift register
232
continuously supplies 1-bit data maintained therein to the exclusive OR circuit
231
. In synchronization with a clock signal, the shift register
232
maintains new 1-bit data supplied from the exclusive OR circuit
231
and supplies the new data to the exclusive OR circuit
231
.
When the convolutional encoder
230
described above receives the 3-bit interleaved data D
203
1
, D
203
2
, and D
203
3
, the convolutional encoder
210
performs a convolutional operation of the interleaved data D
203
1
, D
203
2
, and D
203
3
and outputs the operation result as 3-bit encoded data D
204
1
, D
204
2
, and D
204
3
to the multi-level modulation mapping circuit
240
at the subsequent stage. In other words, the convolutional encoder
230
performs a convolutional operation to encode the inner code with a code rate of 3/3=1 and outputs the generated encoded data D
204
to the multi-level modulation mapping circuit
240
at the subsequent stage.
In synchronization with a clock signal, the multi-level modulation mapping circuit
240
maps the encoded data D
204
output from the convolutional encoder
230
to, for example, an
8
PSK transmission symbol. Specifically, the multi-level modulation mapping circuit
240
maps the 3-bit encoded data D
204
output from the convolutional encoder
230
as a single transmission symbol and generates a single encoded transmission symbol D
205
. The multi-level modulation mapping circuit
240
outputs the generated encoded transmission symbol D
205
to the outside.
In the encoding device
201
described above, the convolutional encoder
210
performs a convolutional operation to encode the outer code with a code rate of 2/3 and the convolutional encoder
230
performs a convolutional operation to encode the inner code with a code rate of 1, resulting in performing a serially concatenated convolutional operation with an overall code rate of (2/
Hattori Masayuki
Miyauchi Toshiyuki
Yamamoto Kohei
Yokokawa Takashi
Sonnenschein Nath & Rosenthal LLP
Sony Corporation
Young Brian
LandOfFree
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