Encoding arrangement for encoding a sequence of (N-1)-bit inform

Coded data generation or conversion – Digital code to digital code converters – To or from fibonacci codes

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341 95, H03M 700

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057607184

ABSTRACT:
Encoding arrangement for encoding a sequence of (n-1)bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1)-bit information words. The encoding arrangement comprises input means for receiving the information words, converter means for converting the (n-1)-bit information words into n-bit channel words and output means for supplying the channel words. The converter means comprises weight vector coefficient supply means for supplying a weight vector w, the weight vector having n weight vector coefficients w.sub.i, where i is an integer running from 1 to n and the weight vector coefficients being in the form of (n-1)-bit binary words, and calculation means for carrying out a calculation using an information word so as to obtain a channel word. The weight vector coefficient supply means is adapted to supply only p bits of a weight vector coefficient w.sub.i, the remaining n-1-p bits of the (n-1)-bit weight vector coefficient word being `zeroes` to be added before or after the p-bit binary word or before and after the p-bit binary word so as to obtain said weight vector coefficient, and that p is an integer smaller than n-1.

REFERENCES:
patent: 4159529 (1979-06-01), Stakhov
patent: 4187500 (1980-02-01), Stakhov et al.
patent: 4792793 (1988-12-01), Rawlinson et al.
patent: 4818969 (1989-04-01), Krakauer et al.
"Fibonacci Codes for Synchronization Control" by William H. Kautz, Trans. IEEE, IT-11, Apr. 1965, pp. 284-291.

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