Coded data generation or conversion – Digital code to digital code converters – To or from 'n' out of 'm' codes
Reexamination Certificate
1999-09-30
2001-09-11
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from 'n' out of 'm' codes
C341S059000, C341S050000, C341S058000, C341S063000, C341S095000, C341S102000, C341S067000, C341S068000, C341S069000, C341S107000, C341S106000, C375S240000, C375S241000, C375S246000, C375S250000, C375S264000, C375S286000
Reexamination Certificate
active
06288657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an encoding apparatus and method, a decoding apparatus and method, and distribution media, and more particularly to an encoding apparatus and method, a decoding apparatus and method, and distribution media for performing encoding and decoding by use of a finite-state transition diagram.
2. Description of the Related Art
A block encoding method is well-known as a conventional recording/encoding method. That is, this method performs block conversion from m-bit data into n-bit code words. In this case, the size of blocks for block conversion has a close relation to the ease of manufacturing an apparatus. An encoding rate is represented by m
; two encoding rates m
=8/10 and m
=10/20 will be considered herein. Although both are the same in encoding rate, the block size in the latter is twice as large.
In the encoding of m
=8/10, 2
8
code words are selected from 2
10
code words. In the encoding of m
=16/20, 2
16
code words are selected from 2
20
code words. In this case, apparently, the latter has more code word candidates and greater freedom. Accordingly, when required restrictions are imposed on codes, more strict conditions can be put on the latter codes. This suggests the possibility that more efficient codes can be generated.
However, the following drawback exists in the above-described block conversion technique. As in an encoder shown in
FIG. 16A and a
decoder shown in
FIG. 16B
, when they are configured with ROM (Random Access Memory), PLA (Programmed Logic Array), or random logic circuits, the circuit size becomes larger like an exponential function for codes of large blocks, e.g., m
=16/20, than for codes of small blocks, e.g., m
=8/10. In other words, for codes of m
=8/10, a table showing a one-to-one correspondence between 2
8
pieces of data and code words are embodied with an encoder and a decoder, while, for codes of m
=16/20, a table showing a one-to-one correspondence between 2
16
pieces of data and code words must be embodied with an encoder and a decoder.
When an encoder and a decoder are configured with a PLA and a random logic circuit, the way of associating data words with code words exerts a great influence on the apparatus size. For codes of small blocks, it is relatively easy to establish a correspondence suitable for apparatus manufacturing, but the larger the block, the more difficult it becomes to find out a correspondence suitable for apparatus manufacturing.
In the logic synthesis by a logic synthesis program, as a block became larger, processing necessary for the synthesis increases like an exponential function and the processing capacity is exceeded, sometimes resulting in failure of the synthesis and requiring a huge amount of time for the synthesis.
SUMMARY OF THE INVENTION
The present invention has been made in view of such circumstances, and its object is to perform encoding and decoding by use of a finite-state transition diagram to make the circuit size small and improve processing speed.
An encoding apparatus as set forth in claim
1
comprises: a first setting means for setting state transition s on a finite-state transition diagram, corresponding to a code; a second setting means for setting a reference value r by use of the state transition s set by the first setting means; a third setting means for setting a pointer p indicating what data word w of the data is being processed; a comparison means for comparing the reference value r set by the second setting means and the value of the pointer p set by the third setting means; and an output means, when it is judged by the comparison means that the pointer p is greater than or equal to the reference value r, for setting the symbol of a code word bit y to either of 1 and 0 and updating the value of the pointer p to (p−r) and outputting it, and when it is judged that the pointer p is smaller than the reference value r, setting the symbol of the code word bit y to the other of 1 and 0 and outputting the value of the pointer p without updating it.
An encoding method as set forth in claim
6
comprises: a first setting step for setting state transition s on a finite-state transition diagram, corresponding to a code; a second setting step for setting a reference value r by use of the state transition s set by the first setting step; a third setting step for setting a pointer p indicating what data word w of the data is being processed; a comparison step for comparing the reference value r set by the second setting step and the value of the pointer p set by the third setting step; and an output means, when it is judged by the comparison step that the pointer p is greater than or equal to the reference value r, for setting the symbol of a code word bit y to either of 1 and 0 and updating the value of the pointer p to (p−r) and outputting it, and when it is judged that the pointer p is smaller than the reference value r, setting the symbol of the code word bit y to the other of 1 and 0 and outputting the value of the pointer p without updating it.
A distribution media as set forth in claim
7
is used to distribute a computer-readable program for executing a process comprising: a first setting step for setting state transition s on a finite-state transition diagram, corresponding to a code; a second setting step for setting a reference value r by use of the state transition s set by the first setting step; a third setting step for setting a pointer p indicating what data word w of the data is being processed; a comparison step for comparing the reference value r set by the second setting step and the value of the pointer p set by the third setting step; and an output means, when it is judged by the comparison step that the pointer p is greater than or equal to the reference value r, for setting the symbol of a code word bit y to either of 1 and 0 and updating the value of the pointer p to (p−r) and outputting it, and when it is judged that the pointer p is smaller than the reference value r, setting the symbol of the code word bit y to the other of 1 and 0 and outputting the value of the pointer p without updating it.
A decoding apparatus as set forth in claim
8
comprises: a first setting means for setting state transition s on a finite-state transition diagram, corresponding to a code; a counting means for counting n as one cycle; a second setting means for setting a reference value r by use of the state transition s set by the first setting means and a counter value i outputted from the counting means; a third setting means for setting a pointer p indicating the minimum value of the range of data to be processed; a judgment means for judging the symbol of a code word bit y; an output means, when it is judged by the judgment means that the symbol of the code word bit y is either of 0 and 1, for updating the value of the pointer p to (p+r) and outputting it, and when it is judged that the symbol of the code word bit y is the other of 0 and 1, outputting the pointer p without updating it; and a determination means for judging whether a counter value i outputted from the counter means is equal to (n−1), and when it is judged that the counter value i is equal to (n−1), determining the pointer p outputted from the output means as a data word w.
A decoding method as set forth in claim
12
comprises: a first setting step for setting state transition s on a finite-state transition diagram, corresponding to a code; a counting step for counting n as one cycle; a second setting step for setting a reference value r by use of the state transition s set by the first setting step and a counter value i outputted from the counting step; a third setting step for setting a pointer p indicating the minimum value of the range of data to be processed; a judgment step for judging the symbol of a code word bit y; an output step, when it is judged by the judgment step that the symbol of the code word bit y is either of 0 and 1, for
Frommer William S.
Frommer Lawrence & Haug LLP.
Mai Lam T.
Sony Corporation
Tokar Michael
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