Encoding and decoding of dual-ported RAM parity using one shared

Details Encoding and decoding of dual-ported RAM parity using one shared Encoding and decoding of dual-ported RAM parity using one shared

1994-08-23

1996-05-07

Beausoliel, Jr., Robert W.

Excavating

39518501, 371 492, G06F 1110

Patent

active

055155065

ABSTRACT:
A parity generation circuit for an internal cache memory of a computer processor. The parity generation circuit generates parity for both reading and writing during execution of a single processor instruction. The parity generation circuit saves processor circuitry by sharing one parity logic tree for both reading and writing. During one clock phase, a multiplexer routes data to the memory through the parity logic tree and a demultiplexer routes parity from the parity logic tree to the memory. During a second clock phase, the multiplexer routes data from the memory through the parity logic tree and the demultiplexer routes parity from the parity logic tree to the processor.

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