Encoding and decoding circuit for run-length-limited coding

Details Encoding and decoding circuit for run-length-limited coding Encoding and decoding circuit for run-length-limited coding

1990-09-07

1993-12-14

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

To or from run length limited codes

341 57, 341100, 341101, 341102, 341106, 360 40, H03M 516, H03M 720, H03M 746, G11B 509

Patent

active

052707148

ABSTRACT:
An encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m
, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system and contains an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers, respectively. Each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder, synchronizing with a clock. The n bits of the output of the encoder is received in parallel in another shift register, and are serially output from the shift register, synchronizing with a second clock. The circuit reduces the maximum required frequency value of its internal clock by operating with only two clock signals. A decoding circuit converts the coded data to the original data.

REFERENCES:
patent: Re30182 (1979-12-01), Howson
patent: 4413251 (1983-11-01), Adler et al.
patent: 4488142 (1984-12-01), Franaszek et al.
patent: 4496934 (1985-01-01), Furukawa
patent: 4551773 (1985-11-01), Cohn et al.
patent: 4577180 (1986-03-01), Fukuda
patent: 4598267 (1986-07-01), Fukuda
patent: 4864303 (1989-09-01), Ofek
patent: 4866544 (1989-09-01), Hashimoto

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