Encoder including an error decision circuit

Details Encoder including an error decision circuit Encoder including an error decision circuit

1992-01-03

1993-12-28

Brinich, Stephen

Facsimile and static presentation processing

Facsimile

Reduced time or bandwidth for static image communication

358136, H04N 712

Patent

active

052744663

ABSTRACT:
An encoder comprises a memory for storing a to-be-coded original image, outputting a to-be-coded image signal in response to a to-be-coded region designation signal for designating a to-be-coded region used as a to-be-coded block, and outputting a to-be-transformed image signal in response to a to-be-transformed region designation signal for designating a to-be-transformed region; a transforming circuit for subjecting the to-be-transformed image signal to a predetermined transformation in response to a transformation method designation signal, and outputting a transformed image signal; a deciding circuit for deciding an error of the transformed image signal with reference to the to-be-coded image signal, and a control circuit for outputting, as a code, information on at least the to-be-transformed region and the transformation method which reduce the error decided by the deciding circuit to a predetermined value or below.

REFERENCES:
patent: 4831659 (1989-05-01), Miyaoka et al.
patent: 4878230 (1989-10-01), Murakami et al.
patent: 4941193 (1990-07-01), Barnsley et al.
patent: 5001560 (1991-03-01), Ericsson
Proceedings of ICASSP 1990, M8.2, IEEE, "A Novel Fractal Block-Coding Technique For Digital Images"; A. E. Jacquin; 1990.

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