Encoder decoder device not using an A/D converter and method the

Coded data generation or conversion – Digital code to digital code converters – With error detection or correction

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369 50, 360 48, H03M 1300

Patent

active

059865920

ABSTRACT:
An encoder/decoder device for improving the bit error rate, speedily and at low cost without using an A/D converter circuit. A comparator compares the playback signal loaded from the disk with a specified reference level, places the signal in binary notation and sends the binary information to a memory. When the continuous length showing the quantity of zeroes placed between ones in succession is an error length which is shorter than a specified length 3T designated beforehand, an error length detection circuit detects this as a continuous length. A pattern detector circuit detects patterns in which the continuous length in front of error length 2T is 3T and the continuous length behind 2T is 4T or more, and further detects patterns in which the next continuous length after error length 2T is 3T and the continuous length in front of 2T is 4T or more. A position compensator circuit specifies the bit right after 2T as the correction position when a pattern greater than 3T-2T-4T is detected; and specifies the bit right before 2T when a pattern greater than 4T-2T-3T is detected. A processing circuit inverts the logic of the bits specified for position correction and outputs the result.

REFERENCES:
patent: 4713802 (1987-12-01), Kobata et al.
patent: 5216677 (1993-06-01), Takagi et al.
patent: 5572496 (1996-11-01), Hayashi et al.
patent: 5701310 (1997-12-01), Deguchi et al.
patent: 5719847 (1998-02-01), Tayeishi et al.
patent: 5771127 (1998-06-01), Reed et al.

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