Encoder and decoder using arithmetic stage to compress code...

Details Encoder and decoder using arithmetic stage to compress code... Encoder and decoder using arithmetic stage to compress code...

2011-07-12

2011-07-12

Nguyen, Khai M (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from code based on probability

C341S056000, C382S247000

Reexamination Certificate

active

07978101

ABSTRACT:
An encoder/decoder architecture including an arithmetic encoder that encodes the MSB portions of a Factorial Pulse Coder output, and that encodes an output of a first-level source encoder, e.g., MDCT. Sub-parts (e.g., frequency bands) of portions (e.g., frames) of the signal are sorted in increasing order based on a measure related to signal energy (e.g., signal energy itself). In a system that overlays Arithmetic Encoding on Factorial Pulse coding, the result is bits re-allocated to bands with higher signal energy content, yielding higher signal quality and higher bit utilization efficiency.

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