Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2011-08-23
2011-08-23
Bullock, Jr., Lewis A (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S550000, C708S497000
Reexamination Certificate
active
08005885
ABSTRACT:
A processor, an instruction set architecture, an instruction, a computer readable medium and a method for implementing optimal per-instruction encoding of rounding control to emulate directed rounding are disclosed. In one embodiment, an apparatus designed to perform directed rounding includes an instruction decoder configured to decode an instruction, which includes a rounding control information to calculate a result boundary. The apparatus also includes a directed rounding emulator configured to adjust the result boundary to form an adjusted result boundary as a function of the rounding control bit. The adjusted result boundary establishes an endpoint for an interval that includes a result. In one embodiment, the directed round emulator is further configured to emulate a round-to-negative infinity rounding mode and a round-to-positive infinity rounding mode based on at least the single rounding control bit.
REFERENCES:
patent: 5450607 (1995-09-01), Kowalczyk et al.
patent: 5680339 (1997-10-01), Moyse et al.
patent: 5812439 (1998-09-01), Hansen
patent: 6035120 (2000-03-01), Ravichandran
patent: 6044392 (2000-03-01), Anderson et al.
patent: 6058410 (2000-05-01), Sharangpani
patent: 6173394 (2001-01-01), Guttag et al.
patent: 6233672 (2001-05-01), Lynch
patent: 7069288 (2006-06-01), Steele, Jr.
patent: 7162621 (2007-01-01), Kissell
patent: 7219117 (2007-05-01), Steele, Jr.
patent: 7236999 (2007-06-01), Steele, Jr.
patent: 7395297 (2008-07-01), Steele, Jr.
patent: 7529912 (2009-05-01), Henry et al.
patent: 2002/0002573 (2002-01-01), Landers et al.
patent: 2008/0012599 (2008-01-01), Hayes
James E. Stine, Michael J. Schulte, “A Combined Interval and Floating Point Multiplier,” glsvlsi, pp. 208, Great Lakes Symposium on VLSI '98, 1998.
Burgess, N., “Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, No. 2, pp. 266-277, Feb. 2005.
Alpha Architecture Handbook, Order No. EC-QD2KB-TE,Digital Equipment Corporation, Maynard, Massachusetts, Oct. 1996, Chapter 4 (pp. 4-74 to 4-156).
H. Ratschek, et al., “Geometry Computations with Interval and New Robust Methods-Applications in Computer Graphics, GIS and Computational Geometry,”Harwood Publishing Limited, © Helmut Ratschek and John Rokne 2003, pp. 19-25.
IA-32 Intel® Architecture Optimization Reference Manual, Order No. 248966-012, Jun. 2005, Chapter 2 (pp. 2-62 to 2-98).
IA-32 Intel® Architecture Software Developer's Manual, Basic Architecture, Order No. 253665-017, Sep. 2005, vol. 1, Chapter 8.1.5 (pp. 8-10 to 8-11).
Bullock, Jr. Lewis A
Cooley LLP
Nvidia Corporation
Sandifer Matthew
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