Encapsulation of ferroelectric capacitors

Details Encapsulation of ferroelectric capacitors Encapsulation of ferroelectric capacitors

2003-01-07

2004-06-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S254000, C438S398000, C438S240000, C438S739000, C257S295000, C257S310000

Reexamination Certificate

active

06746877

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to capacitor encapsulation to prevent hydrogen damage.
BACKGROUND OF THE INVENTION
There have been several integration challenges such as inter-metal dielectrics and passivation to be resolved for realizing commercial ferroelectric random access memory (FeRAM). These problems are mostly due to damage from contaminants, particularly hydrogen damage generated during, for example, back-end processing of IMD, passivation, forming a gas anneal and plasma-TEOS deposition. The hydrogen ions and electrons, impregnated during, for example, the plasma-enhanced chemical vapor deposition (PECVD) process using SiH
4
-based gas chemistry, diffuse into the ferroelectric layers such as PZT or SBT and then pin ferroelectric domains. Moreover, in the worst case, the ferroelectric, as well as certain electrode materials such as SRO (SrRuO
3
) will decompose due to the H
2
attack. Both mechanisms lead to considerable degradation of ferroelectric performance of the FeRAM's capacitor. There are many reports of previous efforts attempting to solve the hydrogen-induced problem. One of the efforts involves the insertion of a proper barrier, for example Al
2
O
3
, directly over the capacitor. However, these efforts have had limited success due to incomplete encapsulation. The barrier does not protect the bottom of the capacitor.
FIGS. 1-3
show a conventional process for encapsulating ferroelectric capacitors.
FIG. 1
shows a wafer
1
following prior art processing steps. A top electrode (TE)
6
is covered with a TEOS (Tetraethyl Orthosilicate) hardmask
2
and mask resist strip patterning is performed using halogen or CO-based chemistry to etch material s such as Iridium, Platinum, Iridium Oxide or various conductive oxide films. A portion of an underlying ferroelectric layer
8
(for example, PZT, SBT, or BLT) is also etched. A FE capacitor
5
is formed from the top electrode
6
, ferroelectric layer
8
and a bottom electrode (BE)
3
as shown in the magnified view of the figure.
A Ti glue-layer
7
serves to adhere the bottom electrode
3
to the substructure of the FE capacitor
5
. The substructure includes a top TEOS layer
15
covering a top nitride layer
9
. Between the Ti glue-layer
7
and the bottom electrode
3
can be layers of Ir (Iridium), IrO
2
(Iridium Oxide) or other materials. A poly silicon contact plug
13
passes through the wafer
1
to form an electrical connection between an active region and the bottom electrode
3
.
Another TEOS hardmask
4
is deposited in preparation for a second etching step. During the second etching step, the ferroelectric layer
8
is further etched along with the bottom electrode
3
. There is a slight over-etch through the top TEOS layer
15
along with any intermediate materials such as the layers of Ir (Iridium) and IrO
2
(Iridium Oxide).
FIG. 2
shows the wafer
1
following this conventional patterning of the bottom electrode
3
.
FIG. 3
shows the prior art insertion of a barrier layer
19
, for example Al
2
O
3
, over the ferroelectric capacitor
5
after the etching steps.
SUMMARY OF THE INVENTION
The present invention provides a ferroelectric capacitor encapsulation method for preventing hydrogen damage to the electrodes and ferroelectric material of the capacitor.
In general terms, the invention is a method for encapsulating a capacitor comprising etching a bottom electrode of a capacitor to expose an underlying wafer surface. Next an undercut is etched between the capacitor and the wafer surface. The undercut is then refilled with a barrier layer to reduce the diffusion of hydrogen from the surface of the wafer into the capacitor.


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