Enabling clock signals with a phase locked loop (PLL) lock detec

Details Enabling clock signals with a phase locked loop (PLL) lock detec Enabling clock signals with a phase locked loop (PLL) lock detec

1996-08-07

1999-03-23

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 2, 331 17, 331 25, 331DIG2, 327143, 327147, 327156, 327299, H03L 7095, H03K 5135

Patent

active

058865829

ABSTRACT:
A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.

REFERENCES:
patent: 5008635 (1991-04-01), Hanke et al.
patent: 5294894 (1994-03-01), Gebara
patent: 5347232 (1994-09-01), Nishimichi
patent: 5467042 (1995-11-01), Smith et al.
Shariatdoust et al. (AT&T Bell Laboratories), IEEE 1992 Custom Integrated Circuits Conference, pp. 24.2.1-24.2.5. "A Low Jitter 5MHz to 180 MHz Clock Synthesizer for Video Graphics".
Alvarez et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 37-38. "A Wide Bandwidth Low-Voltage PLL for Power PC.TM. Micro processors".
Preliminary Data Sheet for Part CY2291, High Performance Data Handbook, Cypress Semiconductor, Pub. May 1995, pp. 10-13 to 10-17.

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