Enabled clock circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307450, 307459, 307596, 307606, 357 16, 364900, H03K 1728

Patent

active

048312860

ABSTRACT:
A GaAs register for storing of digital data is configured with a plurality of "D" type flip-flops having a data terminal and an enable terminal connected to an enabled GaAs clock circuit. The enabled GaAs clock circuit provides a load clock signal to enable the "D" type flip-flops during the loading of data into the plurality of "D" type flip-flops and to prohibit the loading of data without the load clock signal. The enabled GaAs clock circuit has "D" type flip-flop, a clock input circuit and a combining circuit. The clock input circuit receives a clock signal and delays the clock signal. The "D" type flip-flop loads the load enable signal with the rising edge of the clock signal and the delayed clock signal and the loaded enable signal are combined to obtained a combination signal which is used to load data into the plurality of "D" type flip-flops in the register.

REFERENCES:
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patent: 4748417 (1988-05-01), Spengler
Ross et al, "Heterojunction GaAs/GaAlAs Transistors With Enhanced Gain From Avalanche Multiplication", IEEE JSSC, vol. 1, No. 2, pp. 53-56, Jan. 1977.
Tabatabaie-Alavi et al, "Gate Delays of InGaAs/InP Heterojunction Integrated Injection Logic", IEEE EDL, vol. EDL-3, No. 8, Aug. 1982, pp. 200-202.

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