Enable gate for 3 state circuits

Details Enable gate for 3 state circuits Enable gate for 3 state circuits

1982-04-22

1984-08-21

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307473, H03K 1760, H03K 19088

Patent

active

044672233

ABSTRACT:
A circuit for providing a signal which enables the high impedance state of a subsequent three state circuit includes a first circuit portion which provides current to an output node to disable the high impedance state when an input signal is in the first state and a second circuit portion which sinks current from the output node to enable the high impedance state when the input signal is in a second state. The circuit includes an input stage which is directly coupled to a transistor, which transistor simultaneously enables said second circuit portion and disables said first circuit portion when the input signal switches from said second state to said first state.

REFERENCES:
patent: 3510685 (1970-05-01), Watanabe et al.
patent: 3736572 (1973-05-01), Tu
patent: 4042840 (1977-08-01), Chan
patent: 4251737 (1981-02-01), Gaudenzi
patent: 4322640 (1982-03-01), Fukushima et al.
patent: 4413194 (1983-11-01), Birch

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