Emulator for high speed, continuous and discontinuous instructio

Details Emulator for high speed, continuous and discontinuous instructio Emulator for high speed, continuous and discontinuous instructio

1996-03-20

1997-06-03

Lall, Parshotam S.

395568, 395500, G06F 9455

Patent

active

056363753

ABSTRACT:
A jump judgment circuit judges whether an instruction read bus cycle of a CPU to be emulated is to be executed in a sequential order of addresses of a memory. A control circuit operates in accordance with the judgment result. Specifically, if an instruction is in the sequential order of addresses of a memory relative to the immediately preceding instruction, instruction codes previously read from the memory and converted are read from a queue and supplied to the CPU. If an instruction is not in the sequential order of addresses, which would correspond to a jump to a noncontiguous address of a memory, that instruction is read from the memory at the designated address, converted into instruction codes, and supplied to CPU.

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