Emulator chip/board architecture and interface

Details Emulator chip/board architecture and interface Emulator chip/board architecture and interface

2006-07-11

2006-07-11

Rodriguez, Paul L. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

In-circuit emulator

C714S028000

Reexamination Certificate

active

07076420

ABSTRACT:
A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

REFERENCES:
patent: 5202687 (1993-04-01), Distinti
patent: 5371878 (1994-12-01), Coker
patent: 5493723 (1996-02-01), Beck et al.
patent: 5559996 (1996-09-01), Fujioka
patent: 5805792 (1998-09-01), Swoboda et al.
patent: 5889988 (1999-03-01), Held
patent: 5964893 (1999-10-01), Circello et al.
patent: 5999725 (1999-12-01), Barbier et al.
patent: 6032268 (2000-02-01), Swoboda et al.
patent: 6107826 (2000-08-01), Young et al.
patent: 6144327 (2000-11-01), Distinti et al.
patent: 6161199 (2000-12-01), Szeto et al.
patent: 6185522 (2001-02-01), Bakker
patent: 6223144 (2001-04-01), Barnett et al.
patent: 6223272 (2001-04-01), Coehlo et al.
patent: 6263484 (2001-07-01), Yang
patent: 6289300 (2001-09-01), Brannick et al.
patent: 6298320 (2001-10-01), Buckmaster et al.
patent: 6366878 (2002-04-01), Grunert
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6487700 (2002-11-01), Fukushima
patent: 6516428 (2003-02-01), Wenzel et al.
patent: 6564179 (2003-05-01), Belhaj
patent: 6922821 (2005-07-01), Nemecek
patent: 019742577 (1998-11-01), None
Sang-Joom Nam, Jun-Hee Lee, Byong-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Chong-Min Kyung, Kyong-Gu Kang, “Fast Development of Source-level Degugging System Using Hardwrae Emulation”, IEEE 2000, pp. 401-404.
Ing-Jer Huang, Tai-An Lu, “ICEBERG: An Embedded In-cicuit Emulator Synthesizer fro Microcontrollers”, ACM 1999, pp. 580-585.
Ubaid R. Khan, Henery L. Owen, Joseph L.A. Hughes, “FPGA Architectures for ASIC Hardware Emulators”, IEEE 1993, pp. 336-340.
Kyung-Soo Oh, Sang-Yong Yoon, Soo-Ik Chae, “Emulator environment based on an FPGA protoyping board”, IEEE Jun. 21-23, 2000, pp. 72-77.
Jin-Hua Hong, Shin-Arn Hwang, Cheng-Wen Wu, “An FPGA-Based Hardwrae Emulator for Fast Fault Emulation” IEEE 1997 pp. 345-348.
P.C. Ching, Y.H. Cheng, M.H. Ko, “An In-Circuit Emulator for TMS320C25”, IEEE 1994, pp. 51-56.
Dick Pasternak, “In-Circuit-Emulation in ASIC Architecture Core Designs” IEEE 1989, pp. P6-4.1-P6-4.4.
Charles Melear, “Using Backround Modes For Testing, Debugging and Emulation of Microcontrollers”, IEEE 1997, pp. 90-97.
CYPR-CD00182; “In-System Chip Emulator Architecture”; Oct. 10, 2001; U.S. Appl. No. 09/975,115; Snyder et al.
CYPR-CD00183; “Capturing Test/Emulation and Enabling Real-Time Debugging Using FPGA For In-Circuit Emulation”; Oct. 10, 2001; U.S. Appl. No. 09/975,104; Snyder.
CYPR-CD00184; “Host To FPGA Interface In An In-Circuit Emualtion System”; Oct. 10, 2001; U.S. Appl. No. 09/975,105; Nemecek.
CYPR-CD00186; “Method For Breaking Execution Of Test Code In A Dut And Emulator Chip Essentially Simultaneously And Handling Complex Breakpoint Events”; Oct. 10, 2001; U.S. Appl. No. 09/975,338; Nemecek et al.

Affiliated with

Also associated with

Rating

Emulator chip/board architecture and interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Emulator chip/board architecture and interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emulator chip/board architecture and interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3580571