Patent
1997-05-30
1999-09-28
Teska, Kevin J.
39550044, G06F 9455
Patent
active
059601914
ABSTRACT:
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
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Bauer Jerry R.
Bershteyn Mikhail
Butts Michael R.
Sample Stephen P.
Broda Samuel
Quickturn Design Systems Inc.
Teska Kevin J.
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