Emulation system having multiple emulated clock cycles per emula

Details Emulation system having multiple emulated clock cycles per emula Emulation system having multiple emulated clock cycles per emula

1995-06-28

1999-07-13

Teska, Kevin J.

Boots, shoes, and leggings

364578, 364488, 364490, 364491, G06F 1750, G06F 300

Patent

active

059238658

ABSTRACT:
A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled to the inputs of the logic processors. The arrangement of first selectors coupled to shift registers coupled to second selectors coupled to logic processors ensures that uniform routing exists among all of the logic processors in the emulation system. This, in turn, provides a flat programming model so that compilation steps including technology mapping and scheduling are independent of each other, resulting in faster compile times.

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