Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2003-01-24
2004-11-02
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C714S028000, C712S220000
Reexamination Certificate
active
06813703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for emulating a data-driven processor.
2. Description of the Related Art
Research on parallel processing technologies has been proceeding in order to meet the need for higher computer speeds; among them, parallel computers have been important subjects of research. The majority of today's computers are von Neumann processors which fetch and execute instructions serially using a program counter. It is, however, difficult to obtain parallelism in a program for a von Neumann processor. In view of this, research into, and development of, data-driven processors has been carried out in various countries. A data-driven processor is one example of a non-von Neumann processor which executes a program written in the form of a dataflow graph, based on the data-driven concept that any instruction in a program is ready for execution when all the necessary data are available.
In an environment for supporting the development of a data-driven processor, there is a need to provide a system for emulating the operation of the targeted data-driven processor executing a target program. In accomplishing such emulation, it is important to boost the emulation speed by parallel processing. But the reality is that no proposals have ever been made regarding emulation techniques for evaluating pipelined modeling, etc. in a data-driven processor. In addition, an emulation system using a data-driven processor, having an excellent parallel processing capability, has not been proposed.
SUMMARY OF THE INVENTION
The present invention has been devised in view of the above problem, and an object of the invention is to provide an emulation system for data-driven processors, and more particularly, an emulation system that aims at shortening the emulation time by employing parallel processing techniques without increasing overhead.
To achieve the above object, according to a first aspect of the present invention, there is provided a data-driven processor emulation system which, using real data-driven processors, emulates virtual data-driven processors each organized as a pipeline consisting of a sequence of stages, each stage having a data latch for holding a packet, a logic circuit for processing the packet held in the data latch, a self-timed transfer control mechanism for supplying a synchronizing signal to the data latch, and an optional gate logic for controlling, based on processing results from the logic circuit, a SEND signal and an ACK signal transferred between the self-timed transfer control mechanism in the stage and a self-timed transfer control mechanism in a downstream stage, wherein each of the real data-driven processors comprises: data path emulation means for expressing a virtual packet, to be processed in the virtual data-driven processors, as a PACKET message which is a packet to be processed in the real data-driven processor, and for evaluating a processing operation of the virtual packet for each functional block within the virtual data-driven processors; and timing path emulation means for expressing the SEND signal and the ACK signal, to be controlled by the self-timed transfer control mechanism and the gate logic, as a SEND message and an ACK message, respectively, which are packets to be processed in the real data-driven processor, and for evaluating stage-to-stage transfer operation of the SEND signal and the ACK signal.
According to a second aspect of the present invention, the timing path emulation means in the system of the first aspect evaluates the position of the virtual packet at a given time by appending a timestamp to each of the SEND message and the ACK message.
According to a third aspect of the present invention, the timing path emulation means in the system of the first aspect evaluates control operation of the SEND signal and the ACK signal at the gate logic by receiving a CONTROL message representing the result of the evaluation from the data path emulation means.
According to a fourth aspect of the present invention, the data path emulation means in the system of the first aspect processes a plurality of PACKET messages in parallel by assigning a unique identifier to each virtual packet.
According to a fifth aspect of the present invention, the timing path emulation means in the system of the first aspect processes the SEND message and the ACK message in parallel by assigning a unique identifier to each stage.
According to a sixth aspect of the present invention, the system of the first aspect further comprises a von Neumann computer which is connected to the real data-driven processor via a computer network, and which performs processing for generating emulation information and displaying the result of the emulation.
According to a seventh aspect of the present invention, the von Neumann computer in the system of the sixth aspect creates in advance packet flow information concerning each individual virtual packet, and the data path emulation means determines the behavior of the virtual packet by referring to the packet flow information.
According to an eighth aspect of the present invention, the von Neumann computer in the system of the sixth aspect receives, from the real data-driven processor, trace information concerning the position and time of each virtual packet, and displays a pipeline occupancy graph plotting the ratio of the number of stages where packets are present to the total number of stages as a function of time.
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Ito Shinya
Kurebayashi Ryosuke
Nishikawa Hiroaki
Wabiko Yasuhiro
Peikari B. James
Semiconductor Technology Academic Research Center
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