Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2000-01-14
2004-12-28
Homere, Jean R. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S023000, C703S024000, C703S028000, C714S724000, C370S510000
Reexamination Certificate
active
06836757
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is complex integrated circuits including embedded digital processor cores and more particularly in circuit emulation of integrated circuits with embedded digital processor cores.
BACKGROUND OF THE INVENTION
Programmable digital processors such as microprocessors and digital signal processors have become very complex machines. Testing these programmable digital processors has also become complex task. It is now common for semiconductor manufactures to build single integrated circuit programmable digital processors with millions of transistors. The current trend is to devote many of these transistors to on-chip cache memories. Even so, the number of logic circuits and their complex relationships makes testing such integrated circuits an increasingly difficult task.
A trend in electronics makes this testing problem more difficult. Single integrated circuit programmable digital processors are becoming more and more of the electronics of many end products. A single integrated circuit used in this way typically includes a programmable digital processor, read only memory storing the base program, read/write memory for operation and a set of peripherals selected for the particular product. This trend is known as system level integration. In the ultimate system level integration, all the electronics are embodied in a single integrated circuit. This level of integration is now achieved in electronic calculators. Many electronic calculators consist of a single integrated circuit, a keyboard, a display, the battery or solar panel power source and a plastic case. Such integration provides less “visibility” into the operation of the programmable digital signal processor. Because the address and data busses of the digital processor are no longer brought out the device pins, it is more difficult to determine the behavior of the embedded processor from external connections.
Another trend in electronics makes this testing problem more difficult. Many new product applications require differing types of processing. Often control processes and user interface processes are better handled with a different programmable digital processor than digital signal processes. An example is wireless telephones. Many coding/decoding and filtering tasks are best handled by a digital signal processor (DSP). Other tasks such as dialing, controlling user inputs and outputs are best handled by microprocessors such as a RISC (Reduced Instruction Set Computer) processor. There is a trend for a system integrated circuit to include both a RISC processor and a DSP. These two processors will typically operate independently and employ differing instruction set architectures. Thus there may be more than one programmable digital processor on a single integrated circuit, each having limited visibility via the device pins.
Another problem is product emulation when employing these programmable digital processors. Product development and debugging is best handled with an emulation circuit closely corresponding to the actual integrated circuit to be employed in the final product. In circuit emulation (ICE) is in response to this need. An integrated circuit with ICE includes auxiliary circuits not needed in the operating product included solely to enhance emulation visibility. In the typical system level integration circuit, these emulation circuits use only a very small fraction of the number of transistors employed in operating circuits. Thus it is feasible to include ICE circuits in all integrated circuits manufactured. Since every integrated circuit can be used for emulation, inventory and manufacturing need not differ between a normal product and an emulation enhanced product.
As a result of these trends there is a need in the art for integrated circuits which are easier to test and easier to emulate.
SUMMARY OF THE INVENTION
This invention involves emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of the modules is selected for communication. Nonselected modules are made nonresponsive to data on the serial connection. The external emulation hardware supplies a serial signal having a first logic state for a number of cycles greater in number than a number of bits of the serial connection of registers to the test access port. The emulation hardware supplies a start bit having an opposite logic state. The selected module detects the start bit and stores the next predetermined number of data bits. These bits could be data bits to be stored in a program visible data register or bits interpreted as an instruction for execution by the module. The selected module may transmit return communications via the serial scan path using the same format.
REFERENCES:
patent: 5530704 (1996-06-01), Gibbons et al.
patent: 5828824 (1998-10-01), Swoboda
patent: 6037868 (2000-03-01), Oh et al.
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6446230 (2002-09-01), Chung
Landis, D.L; Singh, P., “Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration,” Proceedings of the International Test Conference, 1990 pp.: 120-126.*
Fitch, K.D.; Kane, J., “Application of boundary-scan and full-chip BIST to a 3 ASIC chip set,” Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, pp.: 17.5/1-17.5/4.*
Andrews, J., “An embedded JTAG, system test architecture,” Electro/94 International Conference Proceedings. Combined Volumes, 199, pp.: 691-695.
Brady III W. James
Day Herng-der
Homere Jean R.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
LandOfFree
Emulation system employing serial test port and alternative... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Emulation system employing serial test port and alternative..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emulation system employing serial test port and alternative... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3291260