Emulation of target system interrupts through the use of counter

Details Emulation of target system interrupts through the use of counter Emulation of target system interrupts through the use of counter

1974-04-24

1977-06-21

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 918

Patent

active

040315177

ABSTRACT:
A host system includes a plurality of memory cells, each reserved for a different one of a plurality of peripheral control devices of a target system. During the running of a target system program, the host system being emulated includes means for switching one of the memory cells reserved for a particular peripheral control upon detection of an interrupt condition resulting from the execution of a target system input/output instruction. Each time an interrupt condition causes the switching of one of these cells, the host system increments by one the contents of a counter representative of a bus present in the target system. Each time one of the cells of a bus is reset or cleared, the host system decrements by one the corresponding counter contents. A count of zero stored in the counter simulates the condition of a binary ZERO of providing a logical OR operation upon all of the interrupt signals of the peripheral devices connected to share the same target system bus while a non zero count stored in the counter simulates a binary ONE of performing a logical OR operation upon the interrupt signal lines on the bus.

REFERENCES:
patent: 3546678 (1970-12-01), Callaway et al.
patent: 3560937 (1971-02-01), Fischer
patent: 3596256 (1971-07-01), Alpert et al.
patent: 3599162 (1971-08-01), Byrns et al.
patent: 3665415 (1972-05-01), Beard et al.
patent: 3713109 (1973-01-01), Hornung
patent: 3729716 (1973-04-01), Arulpragasam et al.

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