Boots – shoes – and leggings
Patent
1994-03-02
1995-10-31
Eng, David Y.
Boots, shoes, and leggings
395550, 3649462, 364950, 3642719, G06F 114
Patent
active
054637449
ABSTRACT:
A pulse width modulation circuit in a computer system for emulating a processor operating at a slower instruction execution speed. The pulse width modulator a computer system clock, and a register containing a first value. The first value is user-definable by software and specifies a proportion of time that a processor should remain idle. The apparatus further comprises a counter coupled to the clock, the counter having a range between a second and third values which includes the first value. A comparator is coupled to the counter and the register, and the comparator causes a central processing unit to suspend instruction execution for a specified interval of time. The comparator causes the central processing unit to resume instruction execution for remainder of the counter's range. The processor is therefore kept idle for proportions of time depending on the values of the register and the counter to emulate a slower speed processor. For high performance processors which have an on processor cache, the cache is flushed and disabled.
REFERENCES:
patent: 4451897 (1984-05-01), Murao
patent: 4502117 (1985-02-01), Kihara
patent: 5175844 (1992-12-01), Fukuda
Intel Corporation, Microprocessor and Peripheral Handbook, vol. 1 Microprocessor (1988), pp. 2-1, 2-5, 2-25, 2-89, 2-92, 2-145, 2-151, 2-154, 2-163,2-177, 3-1, 3-4, 4-1, 4-59, 4-84 to 4-86, and 4-91.
Kundu Aniruddha
Oztaskin Ali S.
Eng David Y.
Intel Corporation
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