Emulation of interrupt control mechanism in a multiprocessor sys

Details Emulation of interrupt control mechanism in a multiprocessor sys Emulation of interrupt control mechanism in a multiprocessor sys

1997-04-18

1999-03-30

Teska, Kevin J.

395733, 395737, G06F 9455

Patent

active

058899782

ABSTRACT:
A multiprocessor computer system that includes an emulation feature for lowest priority processor software compatibility while providing fault tolerance includes first and second processors coupled to a system bus that handles transmission of interruption messages within the system. An instruction resulting in an interruption which specifies an interrupt feature causes microcode to generate a trap. A trap handling routine reads ID information from a register of the first processor, and places it in a target processor ID field of an interruption message which gets broadcast on the system bus. The first processor eventually accepts the interruption message and is designated as the processor in the system which handles the interruption.

REFERENCES:
patent: 5440747 (1995-08-01), Kiuchi
patent: 5517626 (1996-05-01), Archer et al.
patent: 5737579 (1998-04-01), Kimura et al.
PSIM -A Simulator for Concurrent Execution of Net-Based Programs, Joerg and Campbell, Feb. 1995.

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