Emulation of circuits with in-circuit memory

Details Emulation of circuits with in-circuit memory Emulation of circuits with in-circuit memory

2007-10-23

2007-10-23

Thangavelu, K. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S024000, C703S025000, C703S028000, C713S152000, C713S400000, C713S401000, C713S002000, C716S030000, C716S030000

Reexamination Certificate

active

10458176

ABSTRACT:
Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

REFERENCES:
patent: 5036473 (1991-07-01), Butts et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 5777489 (1998-07-01), Barbier et al.
patent: 5821773 (1998-10-01), Norman et al.
patent: 5854752 (1998-12-01), Agarwal
patent: 5970240 (1999-10-01), Chen et al.
patent: 6009531 (1999-12-01), Selvidge et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6265894 (2001-07-01), Reblewski et al.
patent: 6463529 (2002-10-01), Miller et al.
patent: 6473726 (2002-10-01), Reblewski
patent: 6539467 (2003-03-01), Anderson et al.
patent: 6694464 (2004-02-01), Quayle et al.
patent: 6697957 (2004-02-01), Wang et al.
patent: 6732068 (2004-05-01), Sample et al.
patent: 2001/0011353 (2001-08-01), Little et al.
patent: 2003/0074178 (2003-04-01), Sample et al.
patent: 2004/0078187 (2004-04-01), Reblewski
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 0 651 343 (1995-05-01), None
patent: WO 94/06210 (1994-03-01), None
Quaiss et al., “Efficient resource arbitration in reconfigurable computing environments”, ACM 2000.
Wu et al., “Fault detection and location of dynamic reconfigurable FPGAs”, IEEE, 1999.
Antoni et al., “Using run-time reconfiguration for fault injection in hardware prototypes”, IEEE 2002.
Antoni et al., “Dependabilty analysis: a new application for run-time reconfiguration”, IEEE 2003.
Nitsch et al., “Embedded system architecture design based on real-time emulation”, IEEE 2000.
Englertet al., “Graceful quorum reconfiguration in a robust emulation of shared memory”, IEEE 2000.
GajjalaPurna et al., “Emulating large designs on small reconfigurable hardware”, IEEE 1998.
Hayashi et al., “Reconfigurable real-time signal transport system using custom FPGs”, IEEE 1995.
Pirola et al., “A solution for hardware emulation of non volatile memory macrocells”, IEEE 2003.
Noguera et al., “Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures”, IEEE 2000.
Charles Clos, “A Study of Non-Blocking Switching Networks”, The Bell System Technical Journal, Mar. 1953, pp. 406-424.
Werner Erhard et al., “First Steps towards a Reconfigurable Asynchronous System”, Friedrich-Schiller University Jena, Department of Computer Science, IEEE International Workshop on Rapid System Prototyping, Jun. 1999, pp. 28-31.
Fatih Kocan et al., “Concurrent D-Algorithm on Reconfigurable Hardware”, IEEE 1999, pp. 152-155.
Jack Jean et al., “Dynamic Reconfiguration to Support Concurrent Applications”, IEEE Transactions Of Computers, vol. 48, No. 6, Jun. 1999, pp. 591-602.
Bernard Bosi et al., “Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 3, Sep. 1999, pp. 299-308.
A. Ejnioui et al., “Design Partitioning on Single-Chip Emulation Systems”, Center for Microelectronics Research, Dept. of CSE, University of South Flordia, 13thInternational Conference on VLSI Design, 2000, pp. 234-239.
Greg Snider, “The Teramac Compiler”, Hewlett-Packard, 1996, pp. 1-51.
Xilinix, “Programmable Gate Array Design Handbook”, First Edition, 1986, pp. i-A10.
Jonathan Babb, et al., “Logic Emulation with Virtual Wires”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jun. 1997, pp. 1-20.

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