Emulation of an m bit counter driven by a desired clock frequenc

Details Emulation of an m bit counter driven by a desired clock frequenc Emulation of an m bit counter driven by a desired clock frequenc

1997-12-12

1999-10-12

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 44, H03K 2100

Patent

active

059664215

ABSTRACT:
An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

REFERENCES:
patent: 4553218 (1985-11-01), Genrich
patent: 5214682 (1993-05-01), Clark

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