Emulation of a high-speed, high-stability clock

Details Emulation of a high-speed, high-stability clock Emulation of a high-speed, high-stability clock

2007-03-06

2007-03-06

Shah, Kamini (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C713S400000, C713S502000, C713S503000, C717S138000

Reexamination Certificate

active

10113121

ABSTRACT:
A method and apparatus for emulating a high-precision, high-accuracy clock. In one embodiment, two clocks are used in the emulation. The first clock has precision greater than precision of the second clock and accuracy less than accuracy of the second clock. A checkpoint time relative to elapsed cycles of the second clock and a checkpoint cycle count of cycles of the first clock are periodically stored relative to a checkpoint period that lasts for a selected number of cycles of the second clock. A reference cycle rate of the first clock is calculated relative to the cycle rate of the second clock. The current time is determined as a function of the checkpoint time, a number of cycles of the first clock elapsed since storing the most recent checkpoint cycle count, and the reference cycle rate of the first clock.

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