Emulating multiple bus used within a data processing system

Details Emulating multiple bus used within a data processing system Emulating multiple bus used within a data processing system

2002-05-10

2010-12-21

Jones, Hugh (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S014000, C703S013000, C703S021000, C703S023000, C703S017000, C716S030000, C702S117000, C700S100000, C700S105000, C700S107000, C700S108000, C700S305000, C700S112000, C700S113000

Reexamination Certificate

active

07856346

ABSTRACT:
A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.

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