Emulated registers

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395825, G06F 9455

Patent

active

057991693

ABSTRACT:
A structure and a method allows I/O or memory addresses of hardware registers to be emulated in software by a central processing unit (CPU). In one embodiment, a first-in-first-out (FIFO) memory is provided to queue read and write operations of the emulated hardware registers. A programmable interrupt mask registers enables certain write operations to the emulated hardware registers to cause an interrupt at the CPU.

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