Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-01-22
2001-03-13
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S693000
Reexamination Certificate
active
06200896
ABSTRACT:
RELATED APPLICATION
This application is related to a co-pending U.S. Patent Application to Koutny entitled “Employing Deionized Water And An Abrasive Surface To Polish A Semiconductor Topography” which is incorporated as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to a method and system for polishing a semiconductor topography in which an acidic liquid substantially free of particulate matter is applied between the semiconductor topography and a surface entrained with abrasive particles.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been formed within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed across the semiconductor topography and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact areas are placed through the dielectric to electrically link the interconnect routing to select impurity regions extending across the substrate. A second level of interconnect routing may be placed across a second level of interlevel dielectric arranged above the first level of interconnect routing. The first and second levels of interconnect routing may be coupled together by contact structures arranged through the second level of interlevel dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed, if desired.
Unfortunately, unwanted surface irregularities (i.e., elevation disparities) occur across the topological surface prior to and after forming a multi-level interconnect structure. For example, a recess may form in the surface of a semiconductor topography during the formation of trench isolation structures within, e.g., a silicon-based substrate. The trench isolation process involves etching a trench within the substrate, followed by chemical-vapor deposition (“CVD”) of a dielectric material into the trench and across the substrate to a level spaced above an upper surface of the substrate. Since the dielectric material accumulates at the same rate upon the base of the trench as well as upon the substrate upper surface laterally outside the trench, a recess will occur in the upper surface of the dielectric material above the trench area. If left unattended, such elevational disparities in the surface of a dielectric layer can lead to various problems. For example, when an interconnect layer is placed across a dielectric surface having elevationally raised and recessed regions, step coverage problems may result. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. Another problem resulting from elevational disparity occurs when subsequent layers are lithographically patterned from the deposited layer. Demarcation between polymerized or non-polymerized photoresist will skew in a lateral dimension as a result of a change in depth-of-focus depending on whether the photoresist resides in an elevational “hill” or “valley” area.
The concept of utilizing chemical and mechanical abrasion to planarize and remove surface irregularities of a topological surface is well known in industry as chemical-mechanical polishing (“CMP”). As shown in
FIG. 1
, a typical CMP process involves placing a semiconductor wafer
12
face-down on a polishing pad
14
which is fixedly attached to a rotatable table or platen
16
. Elevationally extending features of semiconductor wafer
12
are positioned such that they contact the slurry attributed to the CMP process. The polishing pad may be made of various substances, depending on the material being polished. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. An example of a somewhat hard polishing pad is the IC-1000 type pad commercially available from Rodel Products Corporation. A relatively soft pad is the SUBA 500 type pad, also manufactured by Rodel Products Corporation. During the CMP process, polishing pad
14
and semiconductor wafer
12
may be rotated while a carrier
10
holding wafer
12
applies a downward force F upon polishing pad
14
. An abrasive, fluid-based chemical, often referred to as a “slurry”, is deposited upon the surface of polishing pad
14
via a conduit
18
positioned typically above the pad. In this manner, the slurry occupies an interface between pad
14
and the surface of wafer
12
. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The rotational movement of polishing pad
14
relative to wafer
12
causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer
12
. The abrasive slurry particles are typically composed of silica, alumina, or ceria. A polishing apparatus for polishing hard and fragile materials is described in U.S. Pat. No. 5,032,203, which is incorporated herein by reference.
Delivery of the slurry must be carefully monitored so as not to unduly accumulate in select regions of the topography. If too much slurry accumulates in a relatively small area, that area may scratch or, in the extreme, polish at an unacceptably high polish rate. A post-CMP cleaning step is required to remove residual slurry particles from the surface of the polished topography. Without adequately removing the slurry, abrasive slurry particles will remain on the semiconductor topography and contaminate that surface. Considering the minute dimensions of integrated circuit topological features, even the tiniest of defect in the semiconductor topography can render the ensuing integrated circuit inoperable. U.S. Pat. No. 5,320,706 (incorporated herein by reference) describes a method for removing slurry particle residue from a wafer surface by polishing the wafer with a pad while a mixture of deionized water and a surfactant is applied to the wafer and pad. Unfortunately, the removal of such slurry particles may be time consuming and costly. Further, some types of cleaning procedures can be detrimental to the semiconductor topography. The slurry waste must also be disposed of and subjected to waste treatment after planarization is complete because of the toxic nature of some of the effluent components. The disposal and waste treatment of the slurry effluent significantly increases the cost of manufacturing the integrated circuit. Various problems associated with CMP are described in “Chemical-mechanical polishing of interlayer dielectric: A review”, Ali et al., Solid State Technology, October 1994, pp. 63-68 (incorporated herein by reference).
FIGS. 2
,
3
and
4
illustrate the formation of a trench isolation structure within a semiconductor substrate, according to a conventional technique. As shown in
FIG. 2
, a semiconductor substrate
20
comprising, e.g., lightly doped single crystalline silicon is provided. A silicon nitride (“nitride”) layer
24
is arranged across the upper surface of substrate
20
. A “pad” oxide layer
22
may be interposed between substrate
20
and nitride layer
24
to reduce inherent stresses between nitride and silicon. As shown, portions of nitride layer
24
and substrate
20
are etched away to define a trench
21
within substrate
20
. Turning to
FIG. 3
, a fill oxide
26
is then CVD deposited into trench
21
to a level spaced above the upper surface of nitride layer
24
. Prior to depositing fill oxide
26
, a thermally grown oxide liner may be formed at the periphery of trench
21
while nitride layer
24
protects the upper surface of substrate
20
from being oxidized. The resulting upper surface of fill oxide
26
includes a recess
27
arranged above the trench area. A CMP step is then performed to planarize the surface of the semiconductor topography.
As shown
Koutny, Jr. William W. C.
Sethuraman Anantha R.
Conley Rose & Tayon
Cypress Semiconductor Corporation
Daffer Kevin L.
Utech Benjamin L.
Vinh Lan
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